digital-logic-design
Here are 18 public repositories matching this topic...
VHDL codes for UART Interface; hardware communication protocol. contains Receiver & Transmitter units & RAM memory.
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Jun 10, 2021 - VHDL
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
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May 10, 2023 - VHDL
This is a 8 bit binary number multiplier using wallace tree.
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Mar 11, 2018 - VHDL
VHDL Code for Labs done in a 2nd year Digital Systems course at Queen's University.
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Dec 26, 2018 - VHDL
A helicopter game written for the Nexys 4 DDR Board in VHDL
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Dec 13, 2017 - VHDL
Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano
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Sep 11, 2021 - VHDL
Code Archive for Digital Lab (EE 214 @ IITB, Spring 2017)
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Apr 26, 2018 - VHDL
Course Project for EE224 (Digital Systems) offered in Autumn 2023
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Jan 13, 2024 - VHDL
Final examination of Digital Logic Design course (Reti Logiche) - A.Y. 2018/2019 Politecnico di Milano
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Apr 18, 2020 - VHDL
Simple design of interconnected state machines.
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Mar 22, 2018 - VHDL
Xilinx Vivado project for nanoprocessor designing with VHDL
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Sep 4, 2023 - VHDL
This is simple design of finite state machines in Digital Logic Design using VHDL.
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Mar 22, 2018 - VHDL
This project aims to create a network of logic gates that implements a simplified version of the standard algorithm for the histogram equalization method of an image, by recalibrating the contrast of an image when the range of intensity values is very close together.
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Dec 17, 2023 - VHDL
This is the final project for course Digital logic design which is a combination of encryptor, state machines and implementation on Atlys.
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Apr 22, 2018 - VHDL
This was the project assignment for the Digital Logic Design course.
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Mar 24, 2023 - VHDL
This is a digital hardware design of I2C communication protocol using VHDL as the HDL.
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Apr 10, 2023 - VHDL
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