A High-performance Timing Analysis Tool for VLSI Systems
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Updated
May 26, 2023 - Verilog
A High-performance Timing Analysis Tool for VLSI Systems
A Standalone Structural Verilog Parser
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
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