basic implementation of logic structures using verilog (revising github)
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Updated
Feb 29, 2024 - Verilog
basic implementation of logic structures using verilog (revising github)
An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.
CSE-2112 Digital Syatem Design LAb
Digital System Design Lab Codes using Verilog
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.
A repository for some modules I made while learning Verilog
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
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