Fused Multiply Add (FMA) unit Verilog generator written in Python
-
Updated
Apr 26, 2018 - Python
Fused Multiply Add (FMA) unit Verilog generator written in Python
Add a description, image, and links to the fused-multiply-add topic page so that developers can more easily learn about it.
To associate your repository with the fused-multiply-add topic, visit your repo's landing page and select "manage topics."