Systemverilog implementation of an I2C slave with a simple register map. Multi-byte reads and writes supported with address auto-increment.
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Updated
Apr 27, 2024 - SystemVerilog
Systemverilog implementation of an I2C slave with a simple register map. Multi-byte reads and writes supported with address auto-increment.
i2c_slave_tmct is a basic I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices.
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