A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
vhdl
verilog
logic-gates
modelsim
verilog-hdl
logic-circuit
logical-gates
quartus
vhdl-code
logical-circuits
vhdl-examples
verilog-project
quartus2
verilog-code
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Updated
May 24, 2024 - Verilog