HLS for Networks-on-Chip
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Updated
Feb 18, 2021 - C++
HLS for Networks-on-Chip
System-on-Chip Interconnection Network - Simulation Environment (front-end)
Development and simulation framework for Application Specific Vector Processor
HLS code for Network on Chip (NoC)
Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
A Voting Approach for Adaptive Network-on-Chip Power-Gating
System-on-Chip Interconnect Network Simulation Environment back-end (simulator)
Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.
This is a fork of the Network on Chip Simulator - Noxim, enhanced with the capability to inject traffic traces from multiple in-order processors. The infrastructure and traffic injector can be extended to support more complex processors and traces.
Research based implementation of a genetic algorithm for routing 'flits' in an NoC
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