Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
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Updated
Jan 26, 2024 - Verilog
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
(Verilog+FPGA EGO1) (140/100) A real car: our project of CS207 2022 Fall: Digital Logic Design, SUSTech. Taught by Prof. James YU @James-Yu.
SUSTech CS207 Digital Design 2018Fall Materials.
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