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synopsys

Here are 3 public repositories matching this topic...

bojackchen / digital-flow

This is a tutorial on standard digital design flow

synthesis synopsys logic-synthesis verilog-hdl timing-analysis

Updated May 24, 2021
Tcl

kkiningh / synthesis-example

Example of a full DC synthesis script for a simple design

verilog synthesis synopsys vlsi designcompiler

Updated Feb 25, 2019
Tcl

parthpower / DCC_Basic

Typical project for Synopsys DC Compiler

tcl synopsys primetime dc-compiler

Updated Jun 21, 2018
Tcl

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