Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
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Updated
Jun 9, 2021 - Verilog
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
Implementation of a MIPS CPU using Verilog.
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
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