BrianHGinc / BrianHG-DDR3-Controller Star 68 Code Issues Pull requests DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included. fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3 Updated Apr 8, 2024 SystemVerilog
Mahmoud-geberty / Hardware_Design_Projects Star 0 Code Issues Pull requests A repository where I intend to upload most Hardware design projects I make. rtl verilog systemverilog testbenches Updated Jun 28, 2022 SystemVerilog