Fix MMIO IOBinder #1045
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Fix MMIO IOBinder #1045
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jerryz123
reviewed
Nov 15, 2021
| @@ -297,7 +297,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({ | |||
| (system: CanHaveMasterAXI4MMIOPort) => { | |||
| implicit val p: Parameters = GetSystemParameters(system) | |||
| val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) | |||
| clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode) | |||
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I thought the axi4 port takes its clock from the MBus, not the SBus?
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It was on the sbus in the generated RTL I looked at. This seems to confirm, but I could be wrong:
https://github.com/chipsalliance/rocket-chip/blob/86a2f2cca699f149bcc082ef2828654a0a4e3f4b/src/main/scala/subsystem/Ports.scala#L147
jerryz123
approved these changes
Nov 15, 2021
|
@jerryz123 do you know why the tests are getting canceled? |
abejgonzalez
requested changes
Nov 16, 2021
…S. Also adds a config and test
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Thanks for picking up the slack @abejgonzalez |
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Related issue: None
Type of change: bug fix
Impact: rtl change
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