Chipyard Release 1.6.0 (master merge from dev)

[alonamid]

Added

• Diplomatic IOBinder-like approach to setting up PRCI across different deployment targets (Switch PRCI to HarnessBinder/IOBinders #900)
• Default set of MMIO-controlled reset-setters and clock-gaters (Switch PRCI to HarnessBinder/IOBinders #900)
• Added simulation makefile options torture and torture-overnight for running Torture (Add torture run options to makefile #992)
• FSDB waveform support (Add support for FSDB #1072, FSDB support in VLSI flow #1102)
• Use GitHub Actions for CI (Testing GH-A Improvements #1004, Add support for GitHub Actions #999, Run CI only on dev/master/main branches/PRs #1090, Only run CI on pull_requests #1092)
• Add MAKE variable in build-toolchains.sh (Add define for MAKE variable #1021)
• Cleanup GH issue and PR templates (Modify GH Issues (All Feedback Welcome) #1029, Update pull request template (Feedback welcome) #1032)
• Add support for Ibex core (Ibex integration #979)
• Add system bus width fragment (Add WithSystemBusWidth fragment #1071)
• Add support for FSDB waveform files (Add support for FSDB #1072, FSDB support in VLSI flow #1102)
• Document simulator timeout settings (Document simulator-timeout settings #1094)
• Add FFT Generator (MMIO FFT Generator #1067)
• Add waveforms for post-PNR and power (Fix SAIF & Waveforms for Post-P&R Power #1108)
• Have PRCI control registers use clock of corresponding bus (Have PRCI control registers be clocked by the bus they hang off of #1109)
• Add check to verify that user is running on tagged release (Check that Chipyard is running a tagged release #1114)
• Hammer tutorial in Sky130 (Sky130 Tutorial #1115)

Changed

• Bump CVA6 (Bump cva6 #909 )
• Bump Hammer tutorial for ASAP7 r1p7 (ASAP7 r1p7 #934)
• Use Published Chisel, FIRRTL, Treadle, FIRRTLInterpreter packages instead of building from source. Use Published Chisel, FIRRTL, Treadle, FIRRTLInterpreter packages instead of building from source. #1054
• Change serialTL width to 32. Speeds up simulations (Increase default SerialTL width to 32  #1040)
• Update how sbt flag is overridden (by using SBT_BIN variable) (Cleanup how to override SBT + make help documentation update #1041)
• Use published dependencies for Chisel, FIRRTL, Treadle, and FIRRTLInterpreter (Use Published Chisel, FIRRTL, Treadle, FIRRTLInterpreter packages instead of building from source. #1054)
• Split ConfigFragments.scala into multiple files (with more organization) (Split ConfigFragments.scala into multiple files by usage #1061)
• Avoid initializing nvdla software by default (Don't initialize nvdla-workload with init-submodules #1063)
• Update ASAP to 1.7 in Hammer (ASAP7 r1p7 #934)
• Shorten Gemmini docs and point to repo (Shorten the Gemmini Docs #1078)
• Bump Gemmini to 0.6.2 (Bump gemmini to v0.6.2 #1083)
• Use python2 for tracegen script (tracegen: execute to axe script with python2 #1107)
• Bump to Chisel/FIRRTL 3.5.1 (Bump to Chisel 3.5 RC  #1060, Bump dev to master submodule commits #1113)
• Bump to FireMarshal 1.12.1 (bump firemarshal 1.12.1 #1116)
• Bump to FireSim 1.13.0 (Bump FireSim to 1.13.0 #1118 )

Fixed

• Fix UART portmap for Arty (Fixes UART portmap for Arty. #968)
• Support changing make variable MODEL from the cmdline (Fix custom MODEL feature #1030)
• Force FIRRTL to 1.4.1 (Force FIRRTL 1.4.1 #1052)
• Fix MMIO IOBinder (Fix MMIO IOBinder #1045)
• Mask fd warning when running make (Hide which warning when fd isn't installed #1057)
• Fix Sodor 5-stage hazard check (Sodor bump to fixed 5-stage hazard check #1086)
• Fix Sodor val io issue (Bump sodor for val io fix #1089)
• Fix BOOM reference in Readme (Update BOOM reference in README #1104)
• Fix waveforms for post-P&R power analysis (Fix SAIF & Waveforms for Post-P&R Power #1108)

Removed

• Remove duplicate WithUARTIOCells fragment (Remove duplicate WithUARTIOCells [ci skip] #1047)
• Remove MaxPermSize in java variables (Remove MaxPermSize #1082)
• Remove support for CircleCI (Remove CircleCI #1105)