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Increase the throughput of matmuls in WS mode #87

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merged 15 commits into from
Mar 24, 2021

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@hngenc hngenc commented Mar 19, 2021

Together with #85 and #86, this PR is expected to give us near-im2col peformance, without the need for an im2col address generator.

However, the performance will still be lower than with an im2col address generator for those cases where the weight-reuse is low.

@hngenc hngenc closed this Mar 19, 2021
@hngenc hngenc force-pushed the reduce-mesh-with-delays-cycles-in-ws-mode branch from bb077c4 to 8e262b4 Compare March 19, 2021 21:48
@hngenc hngenc reopened this Mar 19, 2021
@hngenc hngenc changed the title [WIP -- DO NOT MERGE] Reduce the latency of a matmul in WS mode [WIP] Reduce the latency of a matmul in WS mode Mar 19, 2021
@hngenc hngenc changed the title [WIP] Reduce the latency of a matmul in WS mode [WIP] Increase the throughput of matmuls in WS mode Mar 24, 2021
@hngenc hngenc changed the title [WIP] Increase the throughput of matmuls in WS mode Increase the throughput of matmuls in WS mode Mar 24, 2021
@hngenc hngenc merged commit b49679d into dev Mar 24, 2021
@hngenc hngenc deleted the reduce-mesh-with-delays-cycles-in-ws-mode branch March 24, 2021 06:56
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