"This repository offers solutions for pattern and number generation using both classes and functions. It's designed specifically for SystemVerilog interview preparation, providing comprehensive examples for coding practices with and without classes."
Also check these links: https://www.edaplayground.com/x/pkZy https://www.edaplayground.com/x/NGpx https://www.edaplayground.com/x/B29W
I have also added code for TLM port connections in UVM. Here are three examples: https://www.edaplayground.com/x/KB__/