Prateek219 patch 1

Utilities/6-bit-ripple_carry_adder.v

@@ -1,14 +1,39 @@
-// 6-bit ripple-carry adder
+//module of 1-bit carry_adder
+
+module fulladder(
+  input X,   
+  input Y, 
+  input C_in, 
+
+  output S, 
+  output C_out
+  );
+
+  wire w1,w2,w3;
+
+  // Computing Sum (S)
+  xor gate_1(w1, X, Y);   //here w1 is result of xor gate respective inputs X,Y
+  xor gate_2(S, w1, C_in);   //here S is result of xor gate respective inputs w1,C_in
+
+  // Computing Carry (C_out)
+  and gate_3(w2, X, Y);    //here w2 is result of and  gate respective inputs X,Y
+  and gate_4(w3, w1, C_in);   //here w3 is result of xor gate respective inputs w1,C_in
+  or gate_5(C_out, w2, w3);   //here C_out is result of or gate respective inputs w2,w3
+
+endmodule
+
+
+//6-bit adder module
 
 module ripple_adder(
   input [5:0] X,
   input [5:0] Y,
-
+  input C_in,
   output [5:0] S,
   output C_out
   );
 
- wire w1, w2, w3, w4, w5;
+ wire w1, w2, w3, w4, w5; //basiclly each wire is associated betwwen 6 full adder working as C_in in next full adder in series
 
  fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
  fulladder u2(X[1], Y[1], w1, S[1], w2);
@@ -17,4 +42,6 @@ module ripple_adder(
  fulladder u5(X[4], Y[4], w4, S[4], w5);
  fulladder u6(X[5], Y[5], w5, S[5], C_out);
 
-endmodule
+endmodule 
+
+

memory/RAM_SP_SR_RW.v

@@ -1,50 +1,31 @@
-//-----------------------------------------------------
-// Design Name : RAM_SP_SR_RW
-// File Name   : RAM_SP_SR_RW.v
-// Function    : Single port Synchronous read and write RAM
-//-----------------------------------------------------
-module RAM_SP_SR_RW #(
-    parameter DATA_WIDTH = 8,
-    parameter ADDR_WIDTH = 8,
-    parameter RAM_DEPTH  = 1 << ADDR_WIDTH
-)
-(
-    clk      , // Clock Input
-    address  , // Address Input
-    data_in  , // Data Input
-    data_out , // Data Output
-    we       , // Write Enable
-    cs       , // Chip select
-);
-
-//--------------Input Ports----------------------- 
-input                  clk      ;
-input                  cs       ;
-input [ADDR_WIDTH-1:0] address  ;
-input                  we       ; 
-input [DATA_WIDTH-1:0] data_in  ;
-
-//--------------Output ports----------------------
-output [DATA_WIDTH-1:0] data_out;
-
-//--------------Internal variables---------------- 
-reg [DATA_WIDTH-1:0] data_out ;
-reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-//--------------Code Starts Here------------------ 
-
-// Memory Write Block 
-always @ (posedge clk) begin
-    if (cs && we) begin
-        mem[address] <= data_in;
-    end
-end
-
-// Memory Read Block 
-always @ (posedge clk) begin
-    if (cs && !we) begin
-        data_out <= mem[address];
-    end
-end
 
+module single_port_sync_ram 
+  # (parameter ADDR_WIDTH = 4,
+     parameter DATA_WIDTH = 32,
+     parameter DEPTH = 16 
+    )
+
+  ( 	input 					clk,
+   		input [ADDR_WIDTH-1:0]	addr,
+   		inout [DATA_WIDTH-1:0]	data,
+   		input 					cs,
+   		input 					we,
+   		input 					oe
+  );
+
+  reg [DATA_WIDTH-1:0] 	tmp_data;
+  reg [DATA_WIDTH-1:0] 	mem [DEPTH:0];
+
+  always @ (posedge clk) begin
+    if (cs & we)
+      mem[addr] <= data;
+  end
+
+  always @ (posedge clk) begin
+    if (cs & !we)
+    	tmp_data <= mem[addr];
+  end
+
+  assign data = cs & oe & !we ? tmp_data : 'hz;
 endmodule
+

memory/testbenches/RAM_SP_SR_RW_tb.v

@@ -1,60 +1,49 @@
-// Testbench for RAM_SP_SR_RW module
-module test #(
-    parameter ADDR_WIDTH = 8,
-    parameter DATA_WIDTH = 8,
-    parameter RAM_DEPTH = 1 << ADDR_WIDTH
-    );
 
-    reg clk;
-    reg cs;
-    reg we;
-    reg  [ADDR_WIDTH-1 : 0] address;
-    reg  [DATA_WIDTH-1 : 0] data_write;
-    wire [DATA_WIDTH-1 : 0] data_read;
-
-    // Instantiating module to be tested
-    RAM_SP_SR_RW #(DATA_WIDTH, ADDR_WIDTH, RAM_DEPTH) RAM (
-        .clk(clk),
-        .address(address),
-        .data_in(data_write),
-        .we(we),
-        .data_out(data_read),
-        .cs(cs)
-    );
-
-
-    // For sanity checking
-    integer i;
-    reg [DATA_WIDTH-1 : 0] received [0:RAM_DEPTH-1] ;
-
-    always #5 clk = ~clk;
-    initial begin
-        // dumping of all variables to file
-        $dumpfile("dump.vcd");
-        $dumpvars(1, test);
-
-        clk <= 0;
-
-        // Writing data into the RAM module to be tested
-        for(i=0; i<RAM_DEPTH; ++i) begin
-            repeat(1) @(negedge clk);
-            address <= i;  we <= 1; cs <=1; data_write <= i;
-        end
-
-        // Reading data from the RAM
-        for(i=0; i<RAM_DEPTH; ++i) begin
-            repeat(1) @(negedge clk);
-            address <= i;  we <= 0; cs <=1;
-
-            // for logging error if any
-            repeat(1) @(posedge clk);
-            #1;
-            if(data_read != i) begin
-               $display("Incorrect data read from address: %d, expected: %d, received: %d", address, i, data_read);
-            end
-        end
-
-        $display("Sanity checks completed");
-        #10 $finish;
+module tb;
+  parameter ADDR_WIDTH = 4;
+  parameter DATA_WIDTH = 16;
+  parameter DEPTH = 16;
+
+  reg clk;
+  reg cs;
+  reg we;
+  reg oe;
+  reg [ADDR_WIDTH-1:0] addr;
+  wire [DATA_WIDTH-1:0] data;
+  reg [DATA_WIDTH-1:0] tb_data;
+
+  single_port_sync_ram #(.DATA_WIDTH(DATA_WIDTH)) u0
+  ( 	.clk(clk),
+                        	.addr(addr),
+                        	.data(data),
+                        	.cs(cs),
+   							.we(we),
+   							.oe(oe)
+                         );
+
+
+  always #10 clk = ~clk;
+  assign data = !oe ? tb_data : 'hz;
+
+  initial begin
+    {clk, cs, we, addr, tb_data, oe} <= 0;
+
+    repeat (2) @ (posedge clk);
+
+    for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
+      repeat (1) @(posedge clk) addr <= i; we <= 1; cs <=1; oe <= 0; tb_data <= $random;
+    end
+
+    for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
+      repeat (1) @(posedge clk) addr <= i; we <= 0; cs <= 1; oe <= 1;
     end
-endmodule
+
+    #20 $finish;
+  end
+
+  initial begin
+    $dumpvars;
+    $dumpfile("dump.vcd");
+  end
+
+endmodule

memory/testbenches/ripple_carry_adder.v

@@ -0,0 +1 @@
+c