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False Signal unoptimizable: circular logic warning #63

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veripoolbot opened this issue Jan 30, 2009 · 2 comments
Open

False Signal unoptimizable: circular logic warning #63

veripoolbot opened this issue Jan 30, 2009 · 2 comments

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@veripoolbot veripoolbot commented Jan 30, 2009


Author Name: Lane Brooks
Original Redmine Issue: 63 from https://www.veripool.org
Original Date: 2009-01-30


See attached test case showing the problem. This example shows how bit 0 of a bus is used to generate bit 1 of the same bus. Verilator is falsly detecting this as circular logic. Also shown in this test case is that this example works if the signals are not part of a bus (the `ifdef T_WORKS section).

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@veripoolbot veripoolbot commented Oct 25, 2010


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2010-10-25T20:07:27Z


Similar UNOPTFLAT woes are also discussed in http://www.veripool.org/boards/2/topics/show/373-UNOPTFLAT-Error

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@veripoolbot veripoolbot commented May 27, 2016


Original Redmine Comment
Author Name: Keith Campbell
Original Date: 2016-05-27T22:14:42Z


Also ran into this problem. I can contribute a very simple reproduction case (attached).
Any known workarounds for building a regular binary tree network? (e.g. a network that sums an input array with parametrizable size)

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