ODIN II: Instantiating more than one module with dual_port_ram inside fails

[kmurray]

Originally reported on Google Code with ID 9

What steps will reproduce the problem?
1. ./odin_II.exe -V test2.v -a sample_arch.xml
2.
3.

What is the expected output? What do you see instead?
Instantiating more than one instance of a module, which contains a dual_port_ram inside,
should work.
Instead, ODIN II errors out with "Missing declaration of this symbol dual_port_ram"

Workaround is to copy-and-paste the module in question with another name. See attached
for example.

What version of the product are you using? On what operating system?
ODIN II version 0.1 (from VTR1.0rc1) under 64-bit Linux


Please provide any additional information below.

Reported by eddie.hung on 2012-01-20 01:01:23

---

- _Attachment: [test2.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-9/comment-0/test2.v)_

[kmurray]

Oops. Missing architecture file (taken from VPR directory)

Reported by eddie.hung on 2012-01-20 01:02:03

---

- _Attachment: [sample_arch.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-9/comment-1/sample_arch.xml)_

[kmurray]

Reported by jeffrey.goeders on 2012-01-20 18:17:44

• Labels added: Module-ODIN

[kmurray]

Thank you for discovering this issue. 

The problem stems from the fact that Odin II currently fails to prefix hard blocks
with the module instance name and simply uses the module name. The original author
of this code must have neglected to include the module instance name when naming the
hard blocks. 

I've got someone looking into it, so it should be fixed soon. 

Reported by andy16666 on 2012-04-18 12:17:13

[mflawn]

Issue unresolved

Attached file and sample_arch.xml to reproduce
test2.v.txt

./odin_II -V test2.v -a ../libs/libarchfpga/arch/sample_arch.xml  

	Optimizing module by AST based optimizations 
	Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)
	==========================
	Detected Top Level Module:      m
	==========================
	-------------- 
	Odin has decided you have failed ;)

	ERROR (1):NETLIST_ERROR (File: test2.v) (Line number: 41) Missing declaration of this symbol dual_port_ram
			  .addr2(addr2));
	ASSERT FAILED:
			@[/mnt/c/Users/casa/vtr-verilog-to-routing/ODIN_II/SRC/ast_util.cpp]get_name_of_pins::813
	Aborted (core dumped)

[jeanlego]

fixed