Do not support the constant shift #38
Labels
bug
Incorrect behaviour
enhancement
Feature enhancement
Good First Issue
Good issues for new or first-time contributors
lang-hdl
Hardware Description Language (Verilog/VHDL)
Odin Elaboration
Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase
Odin Tech.Mapping
Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic
Odin
Odin II Logic Synthesis Tool: Unsorted item
Originally reported on Google Code with ID 45
Reported by
JanetChina.V
on 2012-10-25 19:03:39- _Attachment: [a25_decode.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-45/comment-0/a25_decode.v)_ - _Attachment: [a25_decompile.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-45/comment-0/a25_decompile.v)_ - _Attachment: [debug_functions.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-45/comment-0/debug_functions.v)_
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