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Do not support the constant shift #38

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kmurray opened this issue Jun 26, 2015 · 3 comments
Closed

Do not support the constant shift #38

kmurray opened this issue Jun 26, 2015 · 3 comments
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bug Incorrect behaviour enhancement Feature enhancement Good First Issue Good issues for new or first-time contributors lang-hdl Hardware Description Language (Verilog/VHDL) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic Odin Odin II Logic Synthesis Tool: Unsorted item

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@kmurray
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kmurray commented Jun 26, 2015

Originally reported on Google Code with ID 45

What steps will reproduce the problem?
1. gdb ./odin_II.exe
2.r -V a25/a25_decode.v
3.

What is the expected output? What do you see instead?
When using the right shift operator, it should work. but it doesn't support it with
localparam or arrays.

error:(Line number: 1430) Odin only supports constant shifts at present

Line: 1239(a25_decode.v  (1'd1 << instruction[19:16]))

What version of the product are you using? On what operating system?


Please provide any additional information below.

Reported by JanetChina.V on 2012-10-25 19:03:39


- _Attachment: [a25_decode.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-45/comment-0/a25_decode.v)_ - _Attachment: [a25_decompile.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-45/comment-0/a25_decompile.v)_ - _Attachment: [debug_functions.v](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-45/comment-0/debug_functions.v)_
@kmurray kmurray self-assigned this Jun 26, 2015
@fresh-eggs
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Implementation of such a feature is currently being investigated by Zack and Panos.

@kmurray kmurray added bug Incorrect behaviour Odin Odin II Logic Synthesis Tool: Unsorted item and removed Type-Defect labels Sep 15, 2016
@kmurray kmurray assigned KennethKent and unassigned kmurray Jan 2, 2017
litghost added a commit to litghost/vtr-verilog-to-routing that referenced this issue Apr 2, 2019
@mflawn
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mflawn commented Jun 5, 2019

Still outstanding issue, see attached the file to reproduce:

a25_decode_fix.v.txt

Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation) 
==========================
Detected Top Level Module:      a25_decode
==========================
-------------- 
Odin has decided you have failed ;)

ERROR (1):NETLIST_ERROR (File: a25/a25_decode_fix.v) (Line number: 1239) Odin only supports constant shifts at present

                                                        (instruction[15:0] & (1'd1 << instruction[19:16]));
ASSERT FAILED:
        @[/mnt/c/Users/casa/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp]create_operation_node::4213  
Aborted (core dumped)

@jeanlego jeanlego added enhancement Feature enhancement lang-hdl Hardware Description Language (Verilog/VHDL) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic Good First Issue Good issues for new or first-time contributors labels Apr 1, 2020
@jeanlego
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closing since #1560 add variable shift support

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Labels
bug Incorrect behaviour enhancement Feature enhancement Good First Issue Good issues for new or first-time contributors lang-hdl Hardware Description Language (Verilog/VHDL) Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic Odin Odin II Logic Synthesis Tool: Unsorted item
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