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Complete Constant and Variable Shift Support #1560

Merged
merged 2 commits into from
Sep 24, 2020
Merged

Complete Constant and Variable Shift Support #1560

merged 2 commits into from
Sep 24, 2020

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sdamghan
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Description

  • Moving Constant Shift from partial_mapping to netlist_create_from_ast
  • Supporting the Variable Shift using Barrel Shift design
  • Passing a new variable in the entire netlist_create_from_ast to keep the value of assignment size.
  • Adding benchmarks to cover all possible Shift operation criteria, such as operands' signedness, Arithmetic or Logical and Constant or Variable Shift.

Related Issue

Issue #38

Motivation and Context

Odin-II still has not supported the entire Shift feature which is an essential operation in hardware programming and Verilog. By moving Constant Shift to the netlist_create_from_ast, the netlist node creation for the Constant Shift operation has been removed. Also, this approach adds the Variable Shift which has not been supported yet.

How Has This Been Tested?

  1. make test (ODIN-II)
  2. Basic Regression Tests
  3. Strong Regression Test
  4. Basic Valgrind Memory Tests (also, Valgrind memory tests for all other regression suits)
  5. Sanitized Basic Regression Tests
  6. Odin-II Micro Tests

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@sdamghan
* Moving const shift fom partial_map to netlist_create_from_ast
62ed3f2 
* Supporting variable shift using Barrel shift design

* Keeping the pointers of main inputs, connected to the shift

* Considering the order for input/output connections of SR and ASR

* Padding RHS input with the MSB for SR and ASR

* Removing netlist node creation for constant shift
@sdamghan
* Adding new shift operation benchmarks to test the design
8f45ccd 
* Removing old benchmarks for shift operation

* Regenerating expectation results
@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code lang-hdl Hardware Description Language (Verilog/VHDL) Odin Odin II Logic Synthesis Tool: Unsorted item tests labels Sep 22, 2020
@jeanlego
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good job on this 👍

thanks

@jeanlego jeanlego merged commit 78fcb4d into verilog-to-routing:master Sep 24, 2020
@jeanlego jeanlego mentioned this pull request Sep 24, 2020
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@sdamghan
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good job on this +1

thanks

@jeanlego Thanks for your comments and guidance.

This was referenced Jan 14, 2021
Closed
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@poname poname deleted the SHIFT_feature branch January 17, 2023 17:53
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lang-cpp C/C++ code lang-hdl Hardware Description Language (Verilog/VHDL) Odin Odin II Logic Synthesis Tool: Unsorted item tests
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@sdamghan @jeanlego