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Support packing when modes provide different routing #365

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Support packing when modes provide different routing #365

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mithro
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@mithro mithro commented Jun 14, 2018

This is a work in progress. I'm sending it to get feedback on the change.

This makes the packer work when there are multiple modes which change the routing pattern through a cluster.

The packer will try and pack everything together, then it will fail routing causing it to fall back to checking routing atom-by-atom.

This will then cause the packer to not add the conflicting modes into one cluster.

@probot-autolabeler probot-autolabeler bot added build Build system lang-cpp C/C++ code lang-make CMake/Make code VPR VPR FPGA Placement & Routing Tool labels Jun 14, 2018
@probot-autolabeler probot-autolabeler bot added build Build system lang-cpp C/C++ code lang-make CMake/Make code VPR VPR FPGA Placement & Routing Tool labels Jun 14, 2018
@probot-autolabeler probot-autolabeler bot added build Build system lang-cpp C/C++ code lang-make CMake/Make code VPR VPR FPGA Placement & Routing Tool labels Jun 14, 2018
@mithro mithro changed the title WIP: Support packing when modes provide different routing Support packing when modes provide different routing Jun 14, 2018
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mithro commented Jun 14, 2018

@kmurray I've now fixed it so that in the case of no routing conflicts the speed should be pretty much identical. I guess I just need to add a test here now?

@mithro mithro mentioned this pull request Jun 15, 2018
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mithro commented Jun 15, 2018

This seems to cause failures at the moment;

Test 'vtr_reg_strong' had 30 qor test failures
Test 'vtr_reg_strong' had 1 run failures
Test complete
Error: 31 tests failed!

regression_tests/vtr_reg_strong/strong_fracturable_luts...
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_post_packed_nets: golden = 249 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common device_width: golden = 11 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common device_height: golden = 11 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common min_chan_width: golden = 36 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common routed_wirelength: golden = 1599 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common logic_block_area_total: golden = 0 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common logic_block_area_used: golden = 0 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common min_chan_width_routing_area_total: golden = 316062. result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common min_chan_width_routing_area_per_tile: golden = 2612.08 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_clb: golden = 14 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_io: golden = 99 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_outputs: golden = 130 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_memories: golden = 1 result = -1
[Fail]  k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common num_mult: golden = 0 result = -1
regression_tests/vtr_reg_strong/strong_mcnc...[Pass]
regression_tests/vtr_reg_strong/strong_no_timing...
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common vpr_status: golden = success result = exited with return code 1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_post_packed_nets: golden = 250 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common device_width: golden = 10 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common device_height: golden = 10 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common min_chan_width: golden = 34 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common routed_wirelength: golden = 2330 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common logic_block_area_total: golden = 3.92691e+06 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common logic_block_area_used: golden = 1.08694e+06 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common min_chan_width_routing_area_total: golden = 218071. result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common min_chan_width_routing_area_per_tile: golden = 2180.71 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_clb: golden = 10 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_io: golden = 99 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_outputs: golden = 130 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_memories: golden = 1 result = -1
[Fail]  k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common num_mult: golden = 0 result = -1

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kmurray commented Jun 15, 2018 

Test 'vtr_reg_strong' had 1 run failures

Indicates that tests crashed or exited non-zero (likely shown as 'Fail' earlier in the log). The QoR failures are likely related to that (-1 is a default value).

@probot-autolabeler probot-autolabeler bot added build Build system infra Project Infrastructure lang-cpp C/C++ code lang-make CMake/Make code lang-perl Perl code scripts Utility & Infrastructure scripts tests VPR VPR FPGA Placement & Routing Tool VTR Flow VTR Design Flow (scripts/benchmarks/architectures) lang-netlist labels Jun 15, 2018
@probot-autolabeler probot-autolabeler bot added infra Project Infrastructure lang-cpp C/C++ code lang-netlist lang-perl Perl code scripts Utility & Infrastructure scripts tests VPR VPR FPGA Placement & Routing Tool VTR Flow VTR Design Flow (scripts/benchmarks/architectures) labels Jul 23, 2018
@probot-autolabeler probot-autolabeler bot added infra Project Infrastructure lang-cpp C/C++ code lang-netlist lang-perl Perl code scripts Utility & Infrastructure scripts tests VPR VPR FPGA Placement & Routing Tool VTR Flow VTR Design Flow (scripts/benchmarks/architectures) labels Aug 16, 2018
@mithro
vpr/pack: Change E_DETAILED_ROUTE_END name.
a71f888 
It was too easy to confuse E_DETAILED_ROUTE_END_ONLY and
E_DETAILED_ROUTE_END. Change it to E_DETAILED_ROUTE_INVALID instead.
@mithro
vpr/pack: Add num_modes attribute to t_lb_rr_node.
d0450df
@mithro
vpr/pack: Rework print_route code slightly.
d88f915
@mithro
vpr/pack: Support searching multiple modes.
d1e87f0 
This makes the packer work when there are multiple modes which change
the routing pattern through a cluster. The packer will try and pack
everything together, then it will fail routing causing it to fall back
to checking routing atom-by-atom. This means the packer will not add the
conflicting modes into one cluster.

This fixes the issue with "route through" modes having to be the
"zeroth" mode.

(I think this actually fixes verilog-to-routing#278 too.)
@mithro
Adding test for modes changing affecting packing.
07acb4b
@mithro
vpr/pack: Enable forcing a mode of a block.
8eef90b
@mithro
vpr/pack: Add overflow protection back.
7252d8d
@mithro
vpr/pack: Make print output less verbose.
ac31bfa
@mithro mithro mentioned this pull request Feb 20, 2019
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@mithro mithro mentioned this pull request Mar 26, 2019
Merged
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@mithro mithro closed this Apr 17, 2019
litghost added a commit to litghost/vtr-verilog-to-routing that referenced this pull request Feb 7, 2020
@litghost
Merge pull request verilog-to-routing#365 from SymbiFlow/improve_genf…
5c324d1 
…asm_speed

Improve VTR/genfasm startup
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