Closed
Description
Author Name: Chris Hopkins
Original Redmine Issue: 857 from https://www.veripool.org
Original Date: 2014-12-09
It seems that although it is able to read generate statements it does not represent the generated hierarchy correctly. When it is a generate for on a module instantiation then a single module instance is generated
Using the example code from:
http://search.cpan.org/~wsnyder/Verilog-Perl-3.406/Netlist.pm
The following Verilog(snipped from a module that just instantiates this):
genvar i;
generate for (i=0; i<4; i++) begin : gen_block
test_sub test_sub_x (
.clk (clk ),
.rst_n (rst_n ),
.data_in (data_mid ),
.data_out (data_out[i*2+:2]),
.data_valid (data_valid),
.data_enable (data_enable_1[i])
);
end
endgenerate
generates the following output:
Module test test
input clk
output data_enable
input data_in
output data_out
input data_valid
input rst_n
Cell test_sub_x
.clk(clk)
.data_enable(data_enable_1[i])
.data_in(data_mid)
.data_out(data_out[i*2+:2])
.data_valid(data_valid)
.rst_n(rst_n)
Module test_sub test.test_sub_x
input clk
output data_enable
input data_in
output data_out
input data_valid
input rst_n
Cell test_sub_sub_0
.inny(rst_n)
.outy(rst_n_buf)
Module test_sub_sub test.test_sub_x.test_sub_sub_0
input inny
output outy
Cell u_test_sub
.clk(clk)
.data_enable(data_enable_0)
.data_in(data_in)
.data_out(data_mid)
.data_valid(data_valid)
.rst_n(rst_n)
When in fact this should generate either 4 cells each with a single submodule or a single cell with multiple submodules under it.