vignesh-raghavan / AES128 Public

Notifications You must be signed in to change notification settings
Fork 3
Star 12

Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.

12 stars 3 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 108 Commits
aes_hw		aes_hw
README.md		README.md

Repository files navigation

AES128

Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.

About

Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.

fpga aes-128 verilog altera

Report repository

Releases

No releases published

Packages

No packages published

Languages