A 6-bit, 1GHz, 133.9fJ neural spike sorting absolute-value detector implemented with both CMOS and pass-transistor logic. Layout optimized for regularity and minimal trace length.
Combinational logic for use between clocked cells with period >= 1ns. Vdd can be scaled to higher values in order to accomoodate up to a 2.5GHz clock.
For 1GHz applications, usage was 133.964fJ. For 2.5GHz applications, usage was 396.79fJ.
Our layout occupies 697um^2.