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Indent & syntax script for Verilog and SystemVerilog
vim-scripts/systemverilog.vim--Kanovsky
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This is a mirror of http://www.vim.org/scripts/script.php?script_id=4743 This script is maintained on github at: https://github.com/nachumk/systemverilog.vim Installation instructions for Pathogen can be found here: https://github.com/nachumk/systemverilog.vim#pathogen-install. These scripts indent and highlight SystemVerilog. It is set to load for Verilog and SystemVerilog files. Comments are not touched! No indent is done on comments at all. Don't attempt to comment in the middle of a block comment, it won't know that it is a comment and therefore it will attempt to indent. Two single line statements that have no begin are indented the same: if(a) if(b) c = 1; will actually indent as: if(a) if(b) c = 1; This is because it is not easy to detect infinitely long indents of this sort. By using this convention this type of code can be indented properly.
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Indent & syntax script for Verilog and SystemVerilog
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