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[Fix] Improve CPU backend compatibility for RISC-V #25816

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Sep 30, 2025
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[Fix] Improve CPU backend compatibility for RISC-V #25816

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9 changes: 5 additions & 4 deletions vllm/engine/arg_utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -1160,11 +1160,12 @@ def create_engine_config(

# Set default arguments for V1 Engine.
self._set_default_args(usage_context, model_config)
# Disable chunked prefill for POWER (ppc64le)/ARM/s390x CPUs in V1
# Disable chunked prefill for POWER (ppc64le)/ARM/s390x/RISCV CPUs in V1
if current_platform.is_cpu() and current_platform.get_cpu_architecture(
) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM):
logger.info("Chunked prefill is not supported for ARM and POWER "
"and S390X CPUs; "
) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM,
CpuArchEnum.RISCV):
logger.info("Chunked prefill is not supported for ARM and POWER, "
"S390X and RISC-V CPUs; "
"disabling it for V1 backend.")
self.enable_chunked_prefill = False
assert self.enable_chunked_prefill is not None
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