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vnay01/README.md

Hello there πŸ‘‹

ASIC and FPGA development

I am Vinay, from India and currently, Sweden is my new home!

I have always been interested in electronics and this has led me to explore the field of Application Specific Integrated Circuits ( TLDR: ASIC ) so here I am at the Faculty of Engineering at Lund University for a Master's degree in Embedded Electronics Engineering with a specialization in System-on-Chip Design.

I have experience in mapping algorithms to hardware and FPGA prototyping. During the course of 2021-22, I have developed skills in Digital IC design, DSP design, and performance improvements using pipelining and parallelism ( thanks to projects from the university and some voluntary practice at home! )

I am also curious about security in hardware, which has led me to take a course in Cryptography at my university. My plan is to take the learnings from this course and evaluate their performance on hardware( i.e. throughput, latency, Area, power, etc. )

Skills:

  • Hardware Description Languages: VHDL, Verilog
  • High Level Synthesis: System C
  • Coding: C, Python
  • Sripting: TCL, Linux Bash
  • Modelling: MATLAB
  • Simulation: LTSPICE, Cadence ADE
  • EDA: Altium, EAGLE, Cadence tools
  • FPGA boards: BASYS3, NEXYS4

What am I doing now!?

  • πŸ”­ Working on Hardware Accelerator for CNN on FPGA
  • 🌱 Learning Cryptography and RISC-V
  • πŸ‘― I’m looking for a master thesis in implementation of 5G DSP chain
  • πŸ“« How to reach me: vnay01@gmail.com or drop me a message on LinkedIn

⚑ Fun fact:

I can mix cool cocktails

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  1. MasterThesis MasterThesis Public

    repo contains code for Framework for Automatic Generation of Assertion

    Verilog 2