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A simple HDL implementation of a MIPS processor

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Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
test		test
.gitignore		.gitignore
Makefile		Makefile
PCounter.vhd		PCounter.vhd
RAM.vhd		RAM.vhd
README		README
ROM.vhd		ROM.vhd
SignExtend.vhd		SignExtend.vhd
TestSimulation.png		TestSimulation.png
adder.vhd		adder.vhd
alu.vhd		alu.vhd
alu_decoder.vhd		alu_decoder.vhd
compile.do		compile.do
control_unit.vhd		control_unit.vhd
first.asm		first.asm
lshift.vhd		lshift.vhd
main_decoder.vhd		main_decoder.vhd
mips.do		mips.do
mips_top.vhd		mips_top.vhd
mipstop.vhd		mipstop.vhd
mux2.vhd		mux2.vhd
registerfile.vhd		registerfile.vhd
registerfile2.vhd		registerfile2.vhd
sort.d		sort.d
sort.dat		sort.dat
sort.s		sort.s
sort.spim		sort.spim
sort_compile.do		sort_compile.do
sort_mips.vhd		sort_mips.vhd
sort_wave.do		sort_wave.do
tb_mips.vhd		tb_mips.vhd
tb_mips_generator.vhd		tb_mips_generator.vhd
test_pc_top.jpg		test_pc_top.jpg
test_suite.dat		test_suite.dat
wave.do		wave.do

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A simple implementation of a MIPS processor.

The current design is a single-cycle execution, unlike the pipe-lined
model that is ubiquitous these days.

Most of the code is written using VHDL (I may convert to Verilog later).


Tools:
  MIPS Simulator:  QtSpim
    http://spimsimulator.sourceforge.net/
  VHDL Simulator:  Altera ModelSim
    http://www.altera.com/products/software/quartus-ii/modelsim/qts-modelsim-index.html
  Diagram Generation:  Altera Quartus II / RTL Viewer
    https://www.altera.com/download/software/quartus-ii-we/11.1sp1


Running the Test Bench:
1. Run Altera ModelSim:
  $ ~/altera/11.1/modelsim/linux/vsim
2. Compile the test-bench entities.
  > do compile.do
2. In the Transcript, load the Test Bench top-level entity.
  > vsim tb_mips
3. After the simulator view begins, load the waveforms.
  > do wave.do
4. Start the simulation.
  > run 500 ns
  There will be an error at the end when the PC goes past the last instruction.


Running the Sort Algorithm:
1. Run Altera ModelSim:
  $ ~/altera/11.1/modelsim/linux/vsim
2. Compile the test-bench entities.
  > do sort_compile.do
2. In the Transcript, load the Test Bench top-level entity.
  > vsim sort_mips
3. After the simulator view begins, load the waveforms.
  > do sort_wave.do
4. Start the simulation.
  > run 1000 ns
  There will be an error at the end when the PC goes past the last instruction.