w11 clock rate limited by CACHE-to-CACHE false path

[wfjm]

So far all Series-7 w11a systems ran with 80 MHz clock. The sys_w11_arty design (with DDR memory support via MIG) also achieves timing closure under Vivado 2017.2, but fails (with a small negative slack) under Vivado 2018.3.

The failing data path has

  Source:      SYS70/CACHE/CMEM_DAT1/sv_ram_reg_0/DOADO[1]
  Destination: SYS70/CACHE/CMEM_DAT3/sv_ram_reg_0/DIADI[1]
  via            VMBOX->SEQ->OUNIT->SEQ->DPATH->SEQ->VMBOX

The connectivity of the multiplexers in pdp_dpath in principle allows such a data flow, but pdp11_sequencer will never configure the multiplexers in such a way. So technically this is a false path.

It seems that the placer strategy changed from Vivado 2017.2 to 2018.3 and that 2018.3 is less tolerant to the sub-optimal w11a design.

This will be fixed in a future release, either by setting up an appropriate false_path constraint, or by changing the data path structure.

[wfjm]

The placement strategy in Vivado 2019.1 has apparently changed, and MIG design are apparently even more sensitive to issue #18. The sys_w11_arty design had to be further down-rated to 72 MHz (from 75 MHz).