#ARM LEGv8 in Verilog

Description of a Datapath in verilog, trying to replicate an ARM CPU. There are other repositories that already worked with this, but I wanted to build my own :). The instructions here can be changed as one whishes, something other projects don´t seem to have (or make it complicated). Perfect if you are trying to implement and use it.

For now, I have only the single cycle version and pipelined one. Who knows what I am going to do next? Used for my learning Quest of HDL 🚀. Tried to follow best coding practices, while also creating in separate files the testbenches and each module. I hope this is usefull to anyone.