Implementation of a simplified synthesisable RISC-Processor with a 4 stage pipelining architecture written in VHDL.
The RISC-Processor uses the 4 stage pipelining architecture with seperate instruction and data storage, following the harward architecture. The Design is synthesisable and can be implemented on a FPGA. The origional design is from the Book "VHDL Synthese - Entwurf digitaler Schaltungen und Systeme" (4. Auflage) by Jürgen Reichardt und Bernd Schwarz.
Below the simulation results of the instruction ROM are shown.
