opt_rmdff with init attribute

[gaomy3832]

I am using yosys to handle some verilog code generated from Vivado HLS. The code has some weird style for FSM, and there is a reg with an initial value. After processing the code, I find there is a $dff cell with constant input, and this constant input is equal to the initial value. So I think the cell should be removed by opt_rmdff, but that is not the case. I dive in the code and see that opt_rmdff will skip the dff with init attribute, regardless of whether or not the initial value is equal to the constant. Is there any reason not to do so? If not, I suggest a simple fix to it as

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 5f52bb8..20966fd 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -122,7 +122,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
                goto delete_dff;
        }

-       if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
+       if (sig_d.is_fully_const() && !sig_r.size() && (!has_init || (has_init && val_init == sig_d.as_const()))) {
                RTLIL::SigSig conn(sig_q, sig_d);
                mod->connect(conn);
                goto delete_dff;

[cliffordwolf]

Thanks for the patch! Fixed this and a few similar cases in commit 9041f34.