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Hardware implemented image processing algorithms like Box blur or Gaussian blur on a Basys3 FPGA. Images are stored in BRAM memory of the FPGA board and displayed on the VGA port. Implementation using VHDL language.

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Hardware-implemented-image-processing-algorithms

Hardware implemented image processing algorithms like Box blur or Gaussian blur on a Basys3 FPGA. Images are stored in BRAM memory of the FPGA board and displayed on the VGA port. Implementation using VHDL language.

Implemented Processing Algorithms: * Grayscale * Box Blur * Gaussian Blur * Invert Colors * Swap Colors

Main Block Diagram: schema bloc principala

Final Results: Blur: 20221201_202051

Grayscale: 20221201_202102

Color swap: 20221201_202154

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Hardware implemented image processing algorithms like Box blur or Gaussian blur on a Basys3 FPGA. Images are stored in BRAM memory of the FPGA board and displayed on the VGA port. Implementation using VHDL language.

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