Support genvar inside generate blocks

[NilsGraf]

One more corner case: Original SystemVerilog snippet:

for (genvar i = 0; i < 32; i++) begin : gen_filter
  ...
end

Output of sv2v:

generate
  for (genvar i = 0; (i < 32); i = (i + 1)) begin : gen_filter
    ...                      
  end
endgenerate

However, Yosys has problems with the genvar inside the generate block, saying ERROR: syntax error, unexpected TOK_GENVAR, expecting TOK_ID or '{'. Yosys works fine if I manually change the generated Verilog as follows:

genvar i;
generate
  for (i = 0; (i < 32); i = (i + 1)) begin : gen_filter
    ...                      
  end
endgenerate

An even safer way is shown below, which uses a unique genvar name to avoid possible name collisions with other generate blocks that use the same genvar name:

genvar gen_filter_i;
generate
  for (gen_filter_i = 0; (gen_filter_i < 32); gen_filter_i = (gen_filter_i + 1)) begin : gen_filter
    ...                      
  end
endgenerate

[NilsGraf]

Similarly, regular for-loops have the same issues. Example:

always_comb
  for (int i = 0; i < 32; i++)

Generated Verilog (note the int i inside the for-loop):

always @(*) 
  for (int i = 0; (i < 32); i = (i + 1))

Instead, it should be:

integer i;
always @(*) 
  for (i = 0; (i < 32); i = (i + 1))

[zachjs]

Thanks for the report! I wasn't aware of the restrictions on Verilog for loops. This should now be resolved.

[NilsGraf]

Thank you for the prompt implementation!

[NilsGraf]

This implementation works fine, but there is a problem when there are multiple generate blocks in a file using the same genvar i. In this case, Conformal LEC tool errors out saying that i is redefined.

Could the sv2v tool uniquify all genvars, e.g. by using the name of the generate block, as shown in the above example where genvar i becomes genvar gen_filter_i?