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Merge pull request #90 from awojasinski-nordicsemi/align-nrfx3.0
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Align firmware to nrfx3.0
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@carlescufi
carlescufi authored May 4, 2023
2 parents 99825b3 + fc785ae commit 8209cb2
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Showing 8 changed files with 68 additions and 21 deletions.
4 changes: 2 additions & 2 deletions platform/ext/target/lairdconnectivity/common/bl5340/target_cfg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -755,8 +755,8 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
* This configuration can be done only from secure code, as otherwise those
* register fields are not accessible. That's why it is placed here.
*/
nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);

/* Enable the instruction and data cache (this can be done only from secure
* code; that's why it is placed here).
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6 changes: 5 additions & 1 deletion platform/ext/target/lairdconnectivity/common/core/plat_test.c
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Expand Up @@ -39,6 +39,7 @@
#endif

#define TIMER_RELOAD_VALUE (1*1000*1000)
#define TIMER_FREQ_HZ (1000000)

/* Area used by psa-arch-tests to keep state. */
#define PSA_TEST_SCRATCH_AREA_SIZE (0x400)
Expand All @@ -47,7 +48,10 @@ static void timer_init(NRF_TIMER_Type * TIMER, uint32_t ticks)
{
nrf_timer_mode_set(TIMER, NRF_TIMER_MODE_TIMER);
nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32);
nrf_timer_frequency_set(TIMER, NRF_TIMER_FREQ_1MHz);
nrf_timer_prescaler_set(TIMER,
NRF_TIMER_PRESCALER_CALCULATE(
NRF_TIMER_BASE_FREQUENCY_GET(TIMER),
TIMER_FREQ_HZ));
nrf_timer_cc_set(TIMER, NRF_TIMER_CC_CHANNEL0, ticks);
/* Clear the timer once event is generated. */
nrf_timer_shorts_enable(TIMER, NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK);
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14 changes: 7 additions & 7 deletions platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c
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Expand Up @@ -73,7 +73,7 @@ static int32_t ARM_USARTx_Initialize(ARM_USART_SignalEvent_t cb_event,

uart_resources->tx_count = 0;
uart_resources->rx_count = 0;
uart_resources->hal_cfg = uart_resources->initial_config->hal_cfg;
uart_resources->hal_cfg = uart_resources->initial_config->config;
uart_resources->baudrate = uart_resources->initial_config->baudrate;

uart_resources->initialized = true;
Expand Down Expand Up @@ -131,7 +131,7 @@ static int32_t ARM_USARTx_Send(const void *data, uint32_t num,
}
}
} else {
nrfx_err_t err_code = nrfx_uarte_tx(&uart_resources->uarte, data, num);
nrfx_err_t err_code = nrfx_uarte_tx(&uart_resources->uarte, data, num, 0);
if (err_code == NRFX_ERROR_BUSY) {
return ARM_DRIVER_ERROR_BUSY;
} else if (err_code != NRFX_SUCCESS) {
Expand Down Expand Up @@ -300,13 +300,13 @@ static ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void)

#define DRIVER_USART(idx) \
static nrfx_uarte_config_t UART##idx##_initial_config = { \
.pseltxd = RTE_USART##idx##_TXD_PIN, \
.pselrxd = RTE_USART##idx##_RXD_PIN, \
.pselrts = RTE_USART##idx##_RTS_PIN, \
.pselcts = RTE_USART##idx##_CTS_PIN, \
.txd_pin = RTE_USART##idx##_TXD_PIN, \
.rxd_pin = RTE_USART##idx##_RXD_PIN, \
.rts_pin = RTE_USART##idx##_RTS_PIN, \
.cts_pin = RTE_USART##idx##_CTS_PIN, \
.baudrate = NRF_UARTE_BAUDRATE_115200, \
.interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \
.hal_cfg = { \
.config = { \
.hwfc = NRF_UARTE_HWFC_DISABLED, \
.parity = NRF_UARTE_PARITY_EXCLUDED, \
.stop = NRF_UARTE_STOP_ONE, \
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39 changes: 39 additions & 0 deletions platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h
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Expand Up @@ -241,6 +241,45 @@ void nrfx_critical_section_exit(void);

//------------------------------------------------------------------------------

/**
* @brief Macro for writing back cache lines associated with the specified buffer.
*
* @param[in] p_buffer Pointer to the buffer.
* @param[in] size Size of the buffer.
*/
#define NRFY_CACHE_WB(p_buffer, size) \
do { \
(void)p_buffer; \
(void)size; \
} while (0)

/**
* @brief Macro for invalidating cache lines associated with the specified buffer.
*
* @param[in] p_buffer Pointer to the buffer.
* @param[in] size Size of the buffer.
*/
#define NRFY_CACHE_INV(p_buffer, size) \
do { \
(void)p_buffer; \
(void)size; \
} while (0)

/**
* @brief Macro for writing back and invalidating cache lines associated with
* the specified buffer.
*
* @param[in] p_buffer Pointer to the buffer.
* @param[in] size Size of the buffer.
*/
#define NRFY_CACHE_WBINV(p_buffer, size) \
do { \
(void)p_buffer; \
(void)size; \
} while (0)

//------------------------------------------------------------------------------

/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_CHANNELS_USED 0

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6 changes: 5 additions & 1 deletion platform/ext/target/nordic_nrf/common/core/plat_test.c
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Expand Up @@ -32,12 +32,16 @@
#endif

#define TIMER_RELOAD_VALUE (1*1000*1000)
#define TIMER_FREQ_HZ (1000000)

static void timer_init(NRF_TIMER_Type * TIMER, uint32_t ticks)
{
nrf_timer_mode_set(TIMER, NRF_TIMER_MODE_TIMER);
nrf_timer_bit_width_set(TIMER, NRF_TIMER_BIT_WIDTH_32);
nrf_timer_frequency_set(TIMER, NRF_TIMER_FREQ_1MHz);
nrf_timer_prescaler_set(TIMER,
NRF_TIMER_PRESCALER_CALCULATE(
NRF_TIMER_BASE_FREQUENCY_GET(TIMER),
TIMER_FREQ_HZ));
nrf_timer_cc_set(TIMER, NRF_TIMER_CC_CHANNEL0, ticks);
/* Clear the timer once event is generated. */
nrf_timer_shorts_enable(TIMER, NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK);
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2 changes: 1 addition & 1 deletion platform/ext/target/nordic_nrf/common/core/services/include/tfm_ioctl_core_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ struct tfm_read_service_range {
* @brief Perform a GPIO MCU select operation.
*
* @param pin_number Pin_number.
* @param mcu MCU to control the pin, use nrf_gpio_pin_mcusel_t values.
* @param mcu MCU to control the pin, use nrf_gpio_pin_sel_t values.
* @param[out] result Result of operation
*
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14 changes: 7 additions & 7 deletions platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -76,14 +76,14 @@ tfm_platform_hal_read_service(const psa_invec *in_vec,
return err;
}

#if defined(GPIO_PIN_CNF_MCUSEL_Msk)
#if NRF_GPIO_HAS_SEL
static bool valid_mcu_select(uint32_t mcu)
{
switch (mcu) {
case NRF_GPIO_PIN_MCUSEL_APP:
case NRF_GPIO_PIN_MCUSEL_NETWORK:
case NRF_GPIO_PIN_MCUSEL_PERIPHERAL:
case NRF_GPIO_PIN_MCUSEL_TND:
case NRF_GPIO_PIN_SEL_APP:
case NRF_GPIO_PIN_SEL_NETWORK:
case NRF_GPIO_PIN_SEL_PERIPHERAL:
case NRF_GPIO_PIN_SEL_TND:
return true;
default:
return false;
Expand All @@ -94,7 +94,7 @@ static uint32_t gpio_service_mcu_select(struct tfm_gpio_service_args * args)
{
if (nrf_gpio_pin_present_check(args->mcu_select.pin_number) &&
valid_mcu_select(args->mcu_select.mcu)) {
nrf_gpio_pin_mcu_select(args->mcu_select.pin_number, args->mcu_select.mcu);
nrf_gpio_pin_control_select(args->mcu_select.pin_number, args->mcu_select.mcu);
return 0;
} else {
return -1;
Expand Down Expand Up @@ -128,5 +128,5 @@ tfm_platform_hal_gpio_service(const psa_invec *in_vec, const psa_outvec *out_ve

return TFM_PLATFORM_ERR_SUCCESS;
}
#endif /* defined(GPIO_PIN_CNF_MCUSEL_Msk) */
#endif /* NRF_GPIO_HAS_SEL */

4 changes: 2 additions & 2 deletions platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -771,8 +771,8 @@ enum tfm_plat_err_t spu_periph_init_cfg(void)
* This configuration can be done only from secure code, as otherwise those
* register fields are not accessible. That's why it is placed here.
*/
nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);

/* Enable the instruction and data cache (this can be done only from secure
* code; that's why it is placed here).
Expand Down

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