Add frdm_mcxe31b board basic support

boards/nxp/frdm_mcxe31b/CMakeLists.txt

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_NXP_MCXE31X_BOOT_HEADER)
+  zephyr_library_sources(boot_header/boot_header.c)
+  zephyr_library_include_directories(boot_header)
+endif()

boards/nxp/frdm_mcxe31b/Kconfig

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+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config NXP_MCXE31X_BOOT_HEADER
+	bool "MCXE31x boot header support"
+	default y
+	help
+	  Enable this option to include the MCXE31x boot header in the final
+	  image. The boot header is required for proper operation of the
+	  on-chip bootloader.
+	  See the MCXE31x reference manual for more details.

boards/nxp/frdm_mcxe31b/Kconfig.frdm_mcxe31b

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+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXE31B
+	select SOC_PART_NUMBER_MCXE31BMPB

boards/nxp/frdm_mcxe31b/board.cmake

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXE31B")
+board_runner_args(linkserver "--device=MCXE31B:FRDM-MCXE31B")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nxp/frdm_mcxe31b/board.yml

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+board:
+  name: frdm_mcxe31b
+  full_name: FRDM-MCXE31B
+  vendor: nxp
+  socs:
+    - name: mcxe31b

boards/nxp/frdm_mcxe31b/boot_header/boot_header.c

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+/*
+ * Copyright 2025 NXP
+ *
+ * SPDXLicense-Identifier: Apache-2.0
+ */
+
+#include "boot_header.h"
+#include "fsl_common.h"
+
+/******************************************************************************
+ *  External references
+ ******************************************************************************/
+#if defined(CONFIG_NXP_MCXE31X_BOOT_HEADER) && (CONFIG_NXP_MCXE31X_BOOT_HEADER != 0U)
+
+extern void *const _vector_start;
+
+/******************************************************************************
+ * Boot Header
+ ******************************************************************************/
+typedef struct image_vector_table {
+	uint32_t header;                     /* header                         */
+	uint32_t boot_config;                /* Boot configuration Word        */
+	const uint32_t reserved1;            /* Reserved                       */
+	const uint32_t *cm7_0_start_address; /* Start address of CM7_0 Core    */
+	const uint32_t reserved2;            /* Reserved                       */
+	const uint32_t *reserved3;           /* Reserved                       */
+	const uint32_t reserved4;            /* Reserved                       */
+	const uint32_t *reserved5;           /* Reserved                       */
+	const uint32_t *reserved6;           /* Reserved                       */
+	const uint32_t *lcc_config;          /* Address of LC config           */
+	uint8_t reserved7[216];              /* Reserved for future use        */
+} ivt_t;
+
+/******************************************************************************
+ * SBAF definitions
+ ******************************************************************************/
+/* CM7_0_ENABLE:                                                              */
+/* 0- Cortex-M7_0 application core clock gated after boot                     */
+/* 1- Cortex-M7_0 application core clock un-gated after boot                  */
+#define CM7_0_ENABLE_MASK 1U
+
+/* Control the boot flow of the application:                                  */
+/* 0- Non-Secure Boot- Application image is started by SBAF without any       */
+/*    authentication in parallel to HSE firmware.                             */
+/* 1- Secure Boot- Application image is executed by HSE firmware after the    */
+/*    authentication. SBAF only starts the HSE firmware after successful      */
+/*    authentication.                                                         */
+#define BOOT_SEQ_MASK 8U
+
+/* APP_SWT_INIT: Control SWT0 before starting application core(s):            */
+/* 0- Disable.                                                                */
+/* 1- Enable. SBAF initializes SWT0 before enabling application cores.        */
+/*    SBAF scans this bit only when BOOT_SEQ bit is 0.                        */
+#define APP_SWT_INIT_MASK 32U
+
+/*!
+ * @brief   Sets register field in peripheral configuration structure.
+ * @details This macro sets register field <c>mask</c> in the peripheral
+ *          configuration structure.
+ * @param   mask  Register field to be set.
+ * @note    Implemented as a macro.
+ */
+#define SET(mask) (mask)
+
+/*!
+ * @brief   Clears register field in peripheral configuration structure.
+ * @details This macro clears register field <c>mask</c> in the peripheral
+ *          configuration structure.
+ * @param   mask  Register field to be cleared.
+ * @note    Implemented as a macro.
+ */
+#define CLR(mask) 0
+
+const ivt_t _boot_header __attribute__((used, section(".boot_header"))) = {
+	.header = 0x5AA55AA5,
+	.boot_config = SET(CM7_0_ENABLE_MASK) | /* booting core is core0           */
+		      CLR(BOOT_SEQ_MASK) |     /* unsecure boot is only supported */
+		      CLR(APP_SWT_INIT_MASK),  /* SWT0 is not setup by BAF        */
+	.cm7_0_start_address = (const uint32_t *)&_vector_start,
+	.lcc_config = (const uint32_t *)&lc_config};
+
+/******************************************************************************
+ * Default configurations that can be overridden by strong definitions
+ ******************************************************************************/
+
+__WEAK const boot_lc_config_t lc_config = 0xffffffff;
+
+#endif /* CONFIG_NXP_MCXE31X_BOOT_HEADER */
+/******************************************************************************
+ * End of module
+ ******************************************************************************/

boards/nxp/frdm_mcxe31b/boot_header/boot_header.h

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+/*
+ * Copyright 2025 NXP
+ *
+ * SPDXLicense-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_BOOT_HEADER_H_
+#define ZEPHYR_INCLUDE_BOOT_HEADER_H_
+
+#include "fsl_common.h"
+
+/******************************************************************************
+ * Configuration structure definition                                         *
+ ******************************************************************************/
+
+typedef uint32_t boot_lc_config_t;
+extern const boot_lc_config_t lc_config;
+
+#endif /* ZEPHYR_INCLUDE_BOOT_HEADER_H_ */

boards/nxp/frdm_mcxe31b/doc/index.rst

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+.. zephyr:board:: frdm_mcxe31b
+
+Overview
+********
+The FRDM-MCXE31B board is a design and evaluation platform based on the NXP MCXE31B
+microcontroller (MCU). NXP MCXE31B MCU based on an Arm Cortex-M7 core, running at
+speeds of up to 160 MHz with a 2.97 to 5.5V supply.
+
+Hardware
+********
+
+- MCXE31B Arm Cortex-M7 microcontroller running up to 160 MHz
+- 4MB dual-bank on chip Flash
+- 320KB SRAM + 192KB TCM
+- 2x I2C
+- 6x SPI
+- 16x UART
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, mikroBUS
+
+For more information about the MCXE31B SoC and FRDM-MCXE31B board, see:
+
+- `MCXE31X Datasheet`_
+- `MCXE31X Reference Manual`_
+- `FRDM-MCXE31B Board User Manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high
+bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low
+bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank).
+
+The GPIO controller provides the option to route external input pad interrupts
+to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC.
+By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller,
+unless they are explicity configured to be directed to the WKPU interrupt
+controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,siul2-gpio.yaml`.
+
+To find information about which GPIOs are compatible with each interrupt
+controller, refer to the device reference manual.
+
++-------+-------------+---------------------------+
+| Name  | Function    | Usage                     |
++=======+=============+===========================+
+| PTC16 | GPIO        | Red LED                   |
++-------+-------------+---------------------------+
+| PTB22 | GPIO        | Green LED                 |
++-------+-------------+---------------------------+
+| PTC14 | GPIO        | Blue LED                  |
++-------+-------------+---------------------------+
+| PTE3  | LPUART5_RX  | UART Console              |
++-------+-------------+---------------------------+
+| PTE14 | LPUART5_TX  | UART Console              |
++-------+-------------+---------------------------+
+
+System Clock
+============
+
+The MCXE31B SoC is configured to use PLL running at 160MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The MCXE31B LPUART5 is used for the console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP3.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shorting the jumper JP3.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J14) of the board.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J13, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxe31b
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
+   Hello World! frdm_mcxe31b/mcxe31b
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxe31b
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
+   Hello World! frdm_mcxe31b/mcxe31b
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCXE31X Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXEP172M160FB0.pdf
+
+.. _MCXE31X Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXE31XRM&location=null
+
+.. _FRDM-MCXE31B Board User Manual:
+   https://www.nxp.com/webapp/Download?colCode=UM12330&location=null&isHTMLorPDF=HTML

boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi

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+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXE31BMPB-pinctrl.h>
+
+&pinctrl {
+	eirq0_default: eirq0_default {
+		group1 {
+			pinmux = <PTD5_EIRQ13>;
+			input-enable;
+		};
+	};
+
+	pinmux_lpuart_5: pinmux_lpuart_5 {
+		group1 {
+			pinmux = <PTE14_LPUART5_TX_O>;
+			output-enable;
+		};
+
+		group2 {
+			pinmux = <PTE3_LPUART5_RX>;
+			input-enable;
+		};
+	};
+};