learning about FPGA
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Updated
May 19, 2024 - SystemVerilog
learning about FPGA
An abstraction library for interfacing EDA tools
Machine learning on FPGAs using HLS
HDL support for VS Code
A flexible and scalable development platform for modern FPGA projects.
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
Build Customized FPGA Implementations for Vivado
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
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