W8D1 & W11D2 : Tianle Jiang

W11D2/Arch W11D2 Notes - jtl.md

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+# Arch W11D2 Notes
+
+## Branch Prediction
+
+#### 2-bit dynamic prediction
+
+change prediction only if misprediction twice
+
+#### Correlation Branches
+
+different branch instruction may hash to same 2-bit predictor
+
+solution: four predictors for each hash value, use the behavior of previous 2 branches to determine which to choose. 
+
+#### Tournament Predictor
+
+a 2-bit counter to choose among
+
+- global predictor
+  - 4k entries, indexed by history of  last 12 branches
+- local predictor
+  - 1024 10-bit entries: last 10 outcomes of the entry
+
+#### BHT & BTB
+
+branch history table : help to make prediction
+
+branch target buffer : jump to predicted position quickly
+
+#### Special Case
+
+JALR hard to predict address

W8D1/Arch W8D1 Notes - jtl.md

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+# Arch W8D1 Notes
+
+## Cache Summary
+
+non-blocking cache
+
+hit under N miss (outstanding $\neq$ out-of-order)
+
+- use MSHR(miss status handling register)
+
+## Virtual Memory
+
+Virtual address mechanism:
+
+processor send virutal address $a$
+
+translate to physical address $a'$
+
+- success: visit main memory
+- fail: fault / exception $\to$ search in virtual memory $\to$ send to main memory $\to$ retry translation
+
+
+
+Translation unit
+
+- section (large fixed size)
+- segment (arbitrary size, complicated for programmer and compiler)
+  - fragment
+    - internal (allocated but not used)
+    - external (fragments that cannot be allocated)
+- page (trade off)
+  - small fixed size
+  - reduce internal fragments
+
+
+
+Page
+
+virtual address = virtual page + offset
+
+physical address = physical page + offset
+
+vp $\to$ pp: page table(in physical memory, not accessible itself)
+
+
+
+Virtual addressing cache
+
+query cache (use va) before translation