GitHub - Archaeoraptor/latch: a latch written in VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
.gitattributes		.gitattributes
.gitignore		.gitignore
Fdiv3.vhd		Fdiv3.vhd
LICENSE		LICENSE
README.md		README.md
control.vhd		control.vhd
counter.vhd		counter.vhd
counter6.vhd		counter6.vhd
fdiv.vhd		fdiv.vhd
latch.vhd		latch.vhd
mutli.vhd		mutli.vhd
sele.vhd		sele.vhd
test_all.vhd		test_all.vhd
test_fdiv.vhd		test_fdiv.vhd
test_fdiv3.vhd		test_fdiv3.vhd
test_latch.vhd		test_latch.vhd
test_multi.vhd		test_multi.vhd
test_sel.vhd		test_sel.vhd
频率计.pdf		频率计.pdf

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FPGA频率计

这是一个VHDL的频率计，主要模块有：

分频器
闸门选择
计数器
锁存器
数码管扫描显示

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a latch written in VHDL

fpga vhdl latch

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VHDL 100.0%