ADRV9002 Platform FPGA Architecture

ADRV9002 Platform FPGA Architecture

The kit is configured to interchange data between the Arria® 10 SoC and the ADRV9002's using an LVDS interface over the FMC LPC connector.

ADRV9001/ADRV9002 HDL Reference Design

This design allows controlling, receiving, and transmitting sample streams from/to an ADRV9001/ADRV9002 device through two independent source synchronous interfaces. Supports both CMOS and LVDS interface, but not at the same time. The selection of the I/O standard must be done with a parameter during build.

The design supports SDR or DDR modes in CMOS mode with one of four lanes, as in LVDS mode one or two lane mode. This is runtime selectable.

DAC Interface

• Has DDS
• Has PRBS Generation

ADC Interface

• Has PN checking
• Has Data Formatter
• Has programmable input delay

Software Register Map

Address	IP
0x44A00000	axi_adrv9001 Interface Core
0x44A30000	axi_dmac/axi_adrv9001_rx1_dma
0x44A40000	axi_dmac/axi_adrv9001_rx2_dma
0x44A50000	axi_dmac/axi_adrv9001_tx1_dma
0x44A60000	axi_dmac/axi_adrv9001_tx2_dma

AXI_ADRV9001/AXI_ADRV9002 Interface Core

Interface Core Register Map

The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.

Address		Name	Description
DWORD	BYTE
0x0000	0x0000	RX1 BASE	See the Base (common to all cores) table for more detail
0x0000	0x0000	RX1 COMMON	See the ADC Common table for more detail
0x0000	0x0000	RX1 CHANNELS	See the ADC Channel table for more detail
0x0200	0x0800	RX1 Delay control	See the IO Delay Control table for more detail
0x0400	0x1000	RX2 BASE	See the Base (common to all cores) table for more detail
0x0400	0x1000	RX2 COMMON	See the ADC Common table for more detail
0x0400	0x1000	RX2 CHANNELS	See the ADC Channel table for more detail
0x0600	0x1800	RX2 Delay control	See the IO Delay Control table for more detail
0x0800	0x2000	TX1 BASE	See the Base (common to all cores) table for more detail
0x0800	0x2000	TX1 COMMON	See the DAC Common table for more detail
0x0800	0x2000	TX1 CHANNELS	See the DAC Channel table for more detail
0x1000	0x4000	TX2 BASE	See the Base (common to all cores) table for more detail
0x1000	0x4000	TX2 COMMON	See the DAC Common table for more detail
0x1000	0x4000	TX2 CHANNELS	See the DAC Channel table for more detail
0x1200	0x4800	TDD1	See the Transceiver TDD Control table for more detail
0x1300	0x4C00	TDD2	See the Transceiver TDD Control table for more detail

Base (common to all cores)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x0000	0x0000	REG_VERSION			Version and Scratch Registers
[31:0]	VERSION[31:0]	RO	0x00000000		Version number. Unique to all cores.
0x0001	0x0004	REG_ID			Version and Scratch Registers
	[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH			Version and Scratch Registers
	[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CONFIG			Version and Scratch Registers
	[0]	IQCORRECTION_DISABLE	RO	0x0	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
	[1]	DCFILTER_DISABLE	RO	0x0	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
	[2]	DATAFORMAT_DISABLE	RO	0x0	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
	[3]	USERPORTS_DISABLE	RO	0x0	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
	[4]	MODE_1R1T	RO	0x0	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
	[5]	DELAY_CONTROL_DISABLE	RO	0x0	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
	[6]	DDS_DISABLE	RO	0x0	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
	[7]	CMOS_OR_LVDS_N	RO	0x0	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
	[8]	PPS_RECEIVER_ENABLE	RO	0x0	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
	[9]	SCALECORRECTION_ONLY	RO	0x0	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
0x0004	0x0010	REG_PPS_IRQ_MASK			PPS Interrupt mask
	[0]	PPS_IRQ_MASK	RW	0x1	Mask bit for the 1PPS receiver interrupt
0x0007	0x001c	REG_FPGA_INFO			FPGA device information Intel encoded values Xilinx encoded values
	[31:24]	FPGA_TECHNOLOGY	RO	0x0	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
	[23:16]	FPGA_FAMILY	RO	0x0	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
	[15:8]	SPEED_GRADE	RO	0x0	Encoded value describing the FPGA's speed-grade
	[7:0]	DEV_PACKAGE	RO	0x0	Encoded value describing the device package. The package might affect high-speed interfaces

ADC Common (axi_ad*)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x0010	0x0040	REG_RSTN			ADC Interface Control & Status
	[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
	[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
	[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL			ADC Interface Control & Status
	[3]	SYNC	RW	0x0	Initialize synchronization between multiple ADCs
	[2]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
	[1]	DDR_EDGESEL	RW	0x0	Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
	[0]	PIN_MODE	RW	0x0	Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.
0x0015	0x0054	REG_CLK_FREQ			ADC Interface Control & Status
	[31:0]	CLK_FREQ[31:0]	RO	0x0000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO			ADC Interface Control & Status
	[31:0]	CLK_RATIO[31:0]	RO	0x0000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS			ADC Interface Control & Status
	[3]	PN_ERR	RO	0x0	If set, indicates pn error in one or more channels.
	[2]	PN_OOS	RO	0x0	If set, indicates pn oos in one or more channels.
	[1]	OVER_RANGE	RO	0x0	If set, indicates over range in one or more channels.
	[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DELAY_CNTRL (Deprecated from version 9)			ADC Interface Control & Status
	[17]	DELAY_SEL	RW	0x0	Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.
	[16]	DELAY_RWN	RW	0x0	Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.
	[15:8]	DELAY_ADDRESS[7:0]	RW	0x00	Delay address, the range depends on the interface pins, data pins are usually at the lower range.
	[4:0]	DELAY_WDATA[4:0]	RW	0x0	Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
0x0019	0x0064	REG_DELAY_STATUS (Deprecated from version 9)			ADC Interface Control & Status
	[9]	DELAY_LOCKED	RO	0x0	Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.
	[8]	DELAY_STATUS	RO	0x0	If set, indicates busy status (access pending). The read data may not be valid if this bit is set.
	[4:0]	DELAY_RDATA[4:0]	RO	0x0	Delay read data, current delay value in the elements
0x001A	0x0068	REG_SYNC_STATUS			ADC Synchronization Status register
	[0]	ADC_SYNC	RO	0x0	ADC synchronization status. Will be set to 1 after the synchronization has been completed
0x001C	0x0070	REG_DRP_CNTRL			ADC Interface Control & Status
	[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
	[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
	[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backward compatibility.
0x001D	0x0074	REG_DRP_STATUS			ADC Interface Control & Status
	[17]	DRP_LOCKED	RO	0x0	If set indicates that the DRP has been locked.
	[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
	[15:0]	RESERVED[15:0]	RO	0x00	Reserved for backward compatibility.
0x001E	0x0078	REG_DRP_WDATA			ADC DRP Write Data
	[15:0]	DRP_WDATA[15:0]	RW	0x00	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA			ADC DRP Read Data
	[15:0]	DRP_RDATA[15:0]	RO	0x00	DRP read data (does not include GTX lanes).
0x0022	0x0088	REG_UI_STATUS			User Interface Status
	[2]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
	[1]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
	[0]	UI_RESERVED	RW1C	0x0	Reserved for backward compatibility.
0x0028	0x00a0	REG_USR_CNTRL_1			ADC Interface Control & Status
	[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0029	0x00a4	REG_ADC_START_CODE			ADC Synchronization start word
	[31:0]	ADC_START_CODE[31:0]	RW	0x00000000	This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
0x002E	0x00b8	REG_ADC_GPIO_IN			ADC GPIO inputs
	[31:0]	ADC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the ADC core
0x002F	0x00bc	REG_ADC_GPIO_OUT			ADC GPIO outputs
	[31:0]	ADC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
0x0030	0x00c0	REG_PPS_COUNTER			PPS Counter register
	[31:0]	PPS_COUNTER[31:0]	RO	0x00000000	Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
0x0031	0x00c4	REG_PPS_STATUS		PPS Status register
	[0]	PPS_STATUS	RO	0x0	If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.

ADC Channel (axi_ad*)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x0100	0x0400	REG_CHAN_CNTRL			ADC Interface Control & Status
	[11]	ADC_LB_OWR	RW	0x0	If set, forces ADC_DATA_SEL to 1, enabling data loopback
	[10]	ADC_PN_SEL_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
	[9]	IQCOR_ENB	RW	0x0	if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
	[8]	DCFILT_ENB	RW	0x0	if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
	[6]	FORMAT_SIGNEXT	RW	0x0	if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
	[5]	FORMAT_TYPE	RW	0x0	Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
	[4]	FORMAT_ENABLE	RW	0x0	Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
	[3]	RESERVED	RO	0x0	Reserved for backward compatibility.
	[2]	RESERVED	RO	0x0	Reserved for backward compatibility.
	[1]	ADC_PN_TYPE_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
	[0]	ENABLE	RW	0x0	If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.
0x0101	0x0404	REG_CHAN_STATUS			ADC Interface Control & Status
	[2]	PN_ERR	RW1C	0x0	PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.
	[1]	PN_OOS	RW1C	0x0	PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.
	[0]	OVER_RANGE	RW1C	0x0	If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.
0x0104	0x0410	REG_CHAN_CNTRL_1			ADC Interface Control & Status
	[31:16]	DCFILT_OFFSET[15:0]	RW	0x0000	DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
	[15:0]	DCFILT_COEFF[15:0]	RW	0x0000	DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
0x0105	0x0414	REG_CHAN_CNTRL_2			ADC Interface Control & Status
	[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
	[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0106	0x0418	REG_CHAN_CNTRL_3			ADC Interface Control & Status
	[19:16]	ADC_PN_SEL[3:0]	RW	0x0	Selects the PN monitor sequence type (available only if ADC supports it). - 0x0: pn9a (device specific, modified pn9) - 0x1: pn23a (device specific, modified pn23) - 0x4: pn7 (standard O.150) - 0x5: pn15 (standard O.150) - 0x6: pn23 (standard O.150) - 0x7: pn31 (standard O.150) - 0x9: pnX (device specific, e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
	[3:0]	ADC_DATA_SEL[3:0]	RW	0x0	Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)
0x0108	0x0420	REG_CHAN_USR_CNTRL_1			ADC Interface Control & Status
	[25]	USR_DATATYPE_BE	RO	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[24]	USR_DATATYPE_SIGNED	RO	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[23:16]	USR_DATATYPE_SHIFT[7:0]	RO	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RO	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[7:0]	USR_DATATYPE_BITS[7:0]	RO	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_CHAN_USR_CNTRL_2			ADC Interface Control & Status
	[31:16]	USR_DECIMATION_M[15:0]	RW	0x0000	This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[15:0]	USR_DECIMATION_N[15:0]	RW	0x0000	This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0110	0x0440	REG*_			Channel 1, similar to register 0x100 to 0x10f.
0x0120	0x0480	REG*_			Channel 2, similar to register 0x100 to 0x10f.
0x01F0	0x07c0	REG*_			Channel 15, similar to register 0x100 to 0x10f.

DAC Common (axi_ad*)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x0010	0x0040	REG_RSTN			DAC Interface Control & Status
	[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
	[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
	[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL_1			DAC Interface Control & Status
	[0]	SYNC	RW	0x0	Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.
0x0012	0x0048	REG_CNTRL_2			DAC Interface Control & Status
	[7]	PAR_TYPE	RW	0x0	Select parity even (0x0) or odd (0x1).
	[6]	PAR_ENB	RW	0x0	Select parity (0x1) or frame (0x0) mode.
	[5]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
	[4]	DATA_FORMAT	RW	0x0	Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
	[3:0]	RESERVED[3:0]	NA	0x00	Reserved
0x0013	0x004c	REG_RATECNTRL			DAC Interface Control & Status
	[7:0]	RATE[7:0]	RW	0x00	The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
0x0014	0x0050	REG_FRAME			DAC Interface Control & Status
	[0]	FRAME	RW	0x0	The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.
0x0015	0x0054	REG_STATUS			DAC Interface Control & Status
	[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_STATUS			DAC Interface Control & Status
	[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS			DAC Interface Control & Status
	[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DAC_CLKSEL			DAC Interface Control & Status
	[0]	DAC_CLKSEL	RW	0x0	Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
0x001C	0x0070	REG_DRP_CNTRL			DRP Control & Status
	[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
	[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
	[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001D	0x0074	REG_DRP_STATUS			DAC Interface Control & Status
	[17]	DRP_LOCKED	RO	0x0	If set indicates the MMCM/PLL is locked
	[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
	[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001E	0x0078	REG_DRP_WDATA			DAC Interface Control & Status
	[15:0]	DRP_WDATA[15:0]	RW	0x0000	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA			DAC Interface Control & Status
	[15:0]	DRP_RDATA	RO	0x0000	DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x0022	0x0088	REG_UI_STATUS			User Interface Status
	[1]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
	[0]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
0x0028	0x00a0	REG_USR_CNTRL_1			DAC User Control & Status
	[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x002E	0x00b8	REG_DAC_GPIO_IN			DAC GPIO inputs
	[31:0]	DAC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the DAC core
0x002F	0x00bc	REG_DAC_GPIO_OUT			DAC GPIO outputs
	[31:0]	DAC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

DAC Channel (axi_ad*)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x0100	0x0400	REG_CHAN_CNTRL_1			DAC Channel Control & Status (channel - 0)
	[15:0]	DDS_SCALE_1[15:0]	RW	0x0000	The DDS scale for tone 1. Defines the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (channel_1_fullscale * scale_1) + (channel_2 * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0101	0x0404	REG_CHAN_CNTRL_2			DAC Channel Control & Status (channel - 0)
	[31:16]	DDS_INIT_1[15:0]	RW	0x0000	The DDS phase initialization for tone 1. Defines the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
	[15:0]	DDS_INCR_1[15:0]	RW	0x0000	Defines the resolution of the phase accumulator. Its value can be defined by INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0102	0x0408	REG_CHAN_CNTRL_3			DAC Channel Control & Status (channel - 0)
	[15:0]	DDS_SCALE_2[15:0]	RW	0x0000	The DDS scale for tone 1. Defines the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (channel_1_fullscale * scale_1) + (channel_2 * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0103	0x040c	REG_CHAN_CNTRL_4			DAC Channel Control & Status (channel - 0)
	[31:16]	DDS_INIT_2[15:0]	RW	0x0000	The DDS phase initialization for tone 1. Defines the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
	[15:0]	DDS_INCR_2[15:0]	RW	0x0000	Defines the resolution of the phase accumulator. Its value can be defined by INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0104	0x0410	REG_CHAN_CNTRL_5			DAC Channel Control & Status (channel - 0)
	[31:16]	DDS_PATT_2[15:0]	RW	0x0000	The DDS data pattern for this channel.
	[15:0]	DDS_PATT_1[15:0]	RW	0x0000	The DDS data pattern for this channel.
0x0105	0x0414	REG_CHAN_CNTRL_6			DAC Channel Control & Status (channel - 0)
	[2]	IQCOR_ENB	RW	0x0	if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
	[1]	DAC_LB_OWR	RW	0x0	If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
	[0]	DAC_PN_OWR	RW	0x0	IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
0x0106	0x0418	REG_CHAN_CNTRL_7			DAC Channel Control & Status (channel - 0)
	[3:0]	DAC_DDS_SEL[3:0]	RW	0x00	Select internal data sources (available only if the DAC supports it). - 0x00: internal tone (DDS) - 0x01: pattern (SED) - 0x02: input data (DMA) - 0x03: 0x00 - 0x04: inverted pn7 - 0x05: inverted pn15 - 0x06: pn7 (standard O.150) - 0x07: pn15 (standard O.150) - 0x08: loopback data (ADC) - 0x09: pnX (Device specific e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
0x0107	0x041c	REG_CHAN_CNTRL_8			DAC Channel Control & Status (channel - 0)
	[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
	[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0108	0x0420	REG_USR_CNTRL_3			DAC Channel Control & Status (channel - 0)
	[25]	USR_DATATYPE_BE	RW	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[24]	USR_DATATYPE_SIGNED	RW	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[23:16]	USR_DATATYPE_SHIFT[7:0]	RW	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RW	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[7:0]	USR_DATATYPE_BITS[7:0]	RW	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_USR_CNTRL_4			DAC Channel Control & Status (channel - 0)
	[31:16]	USR_INTERPOLATION_M[15:0]	RW	0x0000	This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
	[15:0]	USR_INTERPOLATION_N[15:0]	RW	0x0000	This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x010A	0x0428	REG_USR_CNTRL_5			DAC Channel Control & Status (channel - 0)
	[0]	DAC_IQ_MODE[0]	RW	0x0	Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.
	[1]	DAC_IQ_SWAP[1]	RW	0x0	Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
0x0110	0x0440	REG*_			Channel 1, similar to registers 0x100 to 0x10f.
0x0120	0x0480	REG*_			Channel 2, similar to registers 0x100 to 0x10f.
0x01F0	0x07c0	REG*_			Channel 15, similar to registers 0x100 to 0x10f.

IO Delay Control (axi_ad*)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x00	0x0000	REG_DELAY_CONTROL_0			Delay Control & Status
	[4:0]	DELAY_CONTROL_IO_0	RW	0x00	Tap value for input/output delay primitive of the first interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value.
0x01	0x0004	REG_DELAY_CONTROL_1			Delay Control & Status
	[4:0]	DELAY_CONTROL_IO_1	RW	0x00	Tap value for input/output delay primitive of the second interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value.
0x02	0x0008	REG*_			Tap value for input/output delay primitive of the third interface line.
0x03	0x000c	REG*_			Tap value for input/output delay primitive of the fourth interface line.
0x0F	0x003c	REG_DELAY_CONTROL_F			Delay Control & Status
	[4:0]	DELAY_CONTROL_IO_F	RW	0x00	Tap value for input/output delay primitive of the last interface line. In general the data and frame lines are controlled with delay primitives, the number of registers of a controller is device specific.

Transceiver TDD Control (axi_ad*)

Address	Bits	Name	Type	Default	Description
DWORD	BYTE
0x0010	0x0040	REG_TDD_CONTROL_0			TDD Control & Status
	[5]	TDD_GATED_TX_DMAPATH	RW	0x0	If this bit is set, the core requests data from the TX DMA, just when the data path is active. Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity.
	[4]	TDD_GATED_RX_DMAPATH	RW	0x0	If this bit is set, the core provides data for the RX DMA, just when the data path is active. Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity.
	[3]	TDD_TXONLY	RW	0x0	If this bit is set- the TDD controller ignores all the TX_* timing registers below and assumes continuous receive operation within a frame.
	[2]	TDD_RXONLY	RW	0x0	If this bit is set- the TDD controller ignores all the RX_* timing registers below and assumes continuous transmit operation within a frame.
	[1]	TDD_SECONDARY	RW	0x0	Enable the secondary transmit/receive on the active frame. If this bit is clear the controller only uses the _1 timing registers below. If this bit is set - the controller uses the _1 and _2 timing registers below.
	[0]	TDD_ENABLE	RW	0x0	If set, enables the TDD controller- software must set this bit after programming all the registers that controls the tdd timing. Any device settings needs to be done (for example bring the AD9361 to the alert state) prior to to setting this bit. The controller keeps the frame counters in reset if this bit is reset. A 0 to 1 transition in this bit starts the frame counter and tdd mode of operation.
0x0011	0x0044	REG_TDD_CONTROL_1			TDD Control & Status
	[7:0]	TDD_BURST_COUNT	RW	0x00	If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and stops.
0x0012	0x0048	REG_TDD_CONTROL_2			TDD Control & Status
	[23:0]	TDD_COUNTER_INIT	RW	0x000000	The controller sets the frame counter to this value when starting TDD operation. This is the starting offset value for the TDD frame counter.
0x0013	0x004c	REG_TDD_FRAME_LENGTH			TDD Control & Status
	[23:0]	TDD_FRAME_LENGTH	RW	0x000000	The frame length is the terminal count for the 10ms counter running at the digital interface clock- as an example for a 245.76MHz clock it is 0x258000.
0x0014	0x0050	REG_TDD_SYNC_TERMINAL_TYPE			TDD Control & Status
	[0]	TDD_SYNC_TERMINAL_TYPE	RW	0x0	Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.
0x0018	0x0060	REG_TDD_STATUS			TDD Control & Status
	[0]	TDD_RXTX_VCO_OVERLAP	RO	0x0	This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.
	[1]	TDD_RXTX_RF_OVERLAP	RO	0x0	This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.
0x0020	0x0080	REG_TDD_VCO_RX_ON_1			TDD Control & Status
	[23:0]	TDD_VCO_RX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time. The controller enables the receive VCO, when the frame count reaches this value. The VCO may have to be enabled before data can be received. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0021	0x0084	REG_TDD_VCO_RX_OFF_1			TDD Control & Status
	[23:0]	TDD_VCO_RX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX VCO powers down at the first time. The controller disables the receive VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0022	0x0088	REG_TDD_VCO_TX_ON_1			TDD Control & Status
	[23:0]	TDD_VCO_TX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time. The controller enables the transmit VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0023	0x008c	REG_TDD_VCO_TX_OFF_1			TDD Control & Status
	[23:0]	TDD_VCO_TX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX VCO powers down at the first time. The controller disables the transmit VCO when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0024	0x0090	REG_TDD_RX_ON_1			TDD Control & Status
	[23:0]	TDD_RX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX data path is activated at the first time. The controller enables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0025	0x0094	REG_TDD_RX_OFF_1			TDD Control & Status
	[23:0]	TDD_RX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX data path is deactivated the first time. The controller disables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0026	0x0098	REG_TDD_TX_ON_1			TDD Control & Status
	[23:0]	TDD_TX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX data path is activated at the first time. The controller enables the transmit chain, when the frame count reaches this value. This register and the TX_DP_ON register controls the delay between the data path being activated and the time to actually push the transmit data through the transmit chain in the device.
0x0027	0x009c	REG_TDD_TX_OFF_1			TDD Control & Status
	[23:0]	TDD_TX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX data path is deactivated at the first time. The controller disables the transmit chain, when the frame count reaches this value. This register and the TX_DP_OFF register controls the delay between the data path being deactivated and the time to actually stop transmitting data through the transmit chain in the device.
0x0028	0x00a0	REG_TDD_RX_DP_ON_1			TDD Control & Status
	[23:0]	TDD_RX_DP_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller starts to accept data from the digital interface for receive.
0x0029	0x00a4	REG_TDD_RX_DP_OFF_1			TDD Control & Status
	[23:0]	TDD_RX_DP_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller stops to accept data from the digital interface for receive.
0x002A	0x00a8	REG_TDD_TX_DP_ON_1			TDD Control & Status
	[23:0]	TDD_TX_DP_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller starts to request data from the system memory for transmit. The data rate is controlled by the TDD controller.
0x002B	0x00ac	REG_TDD_TX_DP_OFF_1			TDD Control & Status
	[23:0]	TDD_TX_DP_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller stop requesting data from the system memory for transmit.
0x0030	0x00c0	REG_TDD_VCO_RX_ON_2			TDD Control & Status
	[23:0]	TDD_VCO_RX_ON_2	RW	0x000000	The secondary pointer for VCO_RX_ON.
0x0031	0x00c4	REG_TDD_VCO_RX_OFF_2			TDD Control & Status
	[23:0]	TDD_VCO_RX_OFF_2	RW	0x000000	The secondary pointer for VCO_RX_OFF.
0x0032	0x00c8	REG_TDD_VCO_TX_ON_2			TDD Control & Status
	[23:0]	TDD_VCO_TX_ON_2	RW	0x000000	The secondary pointer for VCO_TX_ON.
0x0033	0x00cc	REG_TDD_VCO_TX_OFF_2			TDD Control & Status
	[23:0]	TDD_VCO_TX_OFF_2	RW	0x000000	The secondary pointer for VCO_TX_OFF.
0x0034	0x00d0	REG_TDD_RX_ON_2			TDD Control & Status
	[23:0]	TDD_RX_ON_2	RW	0x000000	The secondary pointer for RX_ON.
0x0035	0x00d4	REG_TDD_RX_OFF_2			TDD Control & Status
	[23:0]	TDD_RX_OFF_2	RW	0x000000	The secondary pointer for RX_OFF.
0x0036	0x00d8	REG_TDD_TX_ON_2			TDD Control & Status
	[23:0]	TDD_TX_ON_2	RW	0x000000	The secondary pointer for TX_ON.
0x0037	0x00dc	REG_TDD_TX_OFF_2			TDD Control & Status
	[23:0]	TDD_TX_OFF_2	RW	0x000000	The secondary pointer for TX_OFF.
0x0038	0x00e0	REG_TDD_RX_DP_ON_2			TDD Control & Status
	[23:0]	TDD_RX_DP_ON_2	RW	0x000000	The secondary pointer for RX_DP_ON.
0x0039	0x00e4	REG_TDD_RX_DP_OFF_2			TDD Control & Status
	[23:0]	TDD_RX_DP_OFF_2	RW	0x000000	The secondary pointer for RX_DP_OFF.
0x003A	0x00e8	REG_TDD_TX_DP_ON_2			TDD Control & Status
	[23:0]	TDD_TX_DP_ON_2	RW	0x000000	The secondary pointer for TX_DP_ON.
0x003B	0x00ec	REG_TDD_TX_DP_OFF_2			TDD Control & Status
	[23:0]	TDD_TX_DP_OFF_2	RW	0x000000	The secondary pointer for TX_DP_OFF.

Physical Interface

The following operation modes are supported by the physical layer. CMOS (CSSI) and LVDS (LSSI) selection is done through a synthesis parameter. Other parameter (column B, G, H) can be run time modified preferably while the core is in reset.

A	B	C	D	E	F	G	H
SSI Mode	Lanes/Channel	Seriaization factor/Lane	Max data lane (MHz)	Max Clock (MHz)	Max sample rate for I/Q (MHz)	Data Type	DDS Rate
CSSI 1-lane	1	32	80	80	2.5	SDR	8
CSSI 1-lane	1	32	160	80	5	DDR	4
CSSI 4-lane	4	8	80	80	10	SDR	2
CSSI 4-lane	4	8	160	80	20	DDR	1
LSSI 1-lane	1	32	983.04	491.52	30.72	DDR	4
LSSI 2-lane	2	16	983.04	491.52	61.44	DDR	2

Columns description:

• A - SSI Modes
• B - Data Lanes Per Channel
• C - Serialization factor Per data lane
• D - Max data lane rate(MHz)
• E - Max Clock rate (MHz)
• F - Max Sample Rate for I/Q (MHz)
• G - Data Type
• H - User Interface Clock to Sample Clock ratio (aka DDS Rate) for Xilinx devices

The following equations apply:

where:

• MaxDataLaneRate - number of bits transferred in a second per active lane
• MaxClockRate - represents the source synchronous interface clock frequency
• UserInterfaceClock - represents the frequency of the clock the user interface logic is connected
• InternalDivider - epresents the division factor the source synchronous interface clock is divided to get the user interface clock. This is implementation specific. CMOS = 1

Since the UserInterfaceClock is an integer multiple (column H) of the MaxSampleRateForIQ the interface toward the user logic has a valid qualifier which is not active on every clock cycle.

Configure DAC common interface

Register 0x0048 REG_CNTRL_2

• [12:8] - NUM_LANES (new) - number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
• [16] - SDR_DDR_N (new) - interface type (1 represents SDR, 0 represents DDR)

Register 0x04c REG_RATECNTRL

• [7:0] RATE - must be set according to column H of the table

Configure ADC common interface

Register 0x0044 REG_CNTRL

• [12:8] - NUM_LANES (new) - number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
• [16] - SDR_DDR_N (new) - interface type ( 1 represents SDR, 0 represents DDR)

Requirements

• Rx1 clock and Rx2 clock should be length matched
• Clock and data in SSI interface must be length matched

Physical interface

RX Component mode

For Rx interfaces the source synchronous associated clock is used to sample the input data. Software configuration is required described in Configure ADC common interface section. Input delays of the FPGA or output delays of the ADRV9001 can be tuned by software for optimize sampling.

TX Using dedicated clock

For Tx interfaces the clock received from the transceiver is used to drive the output data. Software configuration is required for clock rate selection described in Configure DAC common interface section. Input delays of the ADRV9001 can be tuned by software for optimize sampling.

---

Return to Platform Architecture Table of Contents