Skip to content

ADRV9375 Platform User Guide

nnaufel edited this page Jun 9, 2020 · 9 revisions
Clone this wiki locally

Introduction

The ADRV9375 Platform is a complete development platform for applications that require high-performance radios over a wideband frequency range. It connects an Intel Arria® 10 SoC FPGA to an ADRV9375 evaluation board by using the space-saving high-speed JESD204B serial interface.

The Arrow High-Speed Radio Card Development Board is a complete development platform for applications that require high-performance radios over a wideband frequency range, with the space-saving high-speed GSPS JESD204B serial interface. Featuring Analog Devices’ AD9375, a highly integrated wideband RF transceiver with integrated synthesizers and DSP functions, and the Intel Arria 10 SoC FPGA on the Critical Link MitySOM®-A10S, the kit allows them to communicate across 4 serial lanes in each direction at speeds of up to 6.144Gbps per lane. Also provided are all the timing and power components required to both develop solutions and demonstrate the capabilities of JESD204B.

With lane rates up to 6.144Gbps this is the ideal platform for developing a wide range of applications including:

  • 3G/4G micro and macro base stations
  • 3G/4G multicarrier picocells
  • FDD and TDD antenna systems
  • Microwave NLOS backhaul systems
  • Test and measurement applications
  • Software defined radios (SDR)

Table of Contents

  1. Quick Start Guide
  2. Platform Architecture
  3. Build the Example Design

Return to Arrow Highspeed Converter Platforms Home