Improved emulation of ST7789 LCD controller

[calc84maniac]

Implemented many features as documented in the Sitronix datasheet, as well as based on research of the actual behavior on real hardware.

New features:

• MCU and VSYNC display modes, which scan the display using the LCD's internal clock
• Porch control for RGB display mode, as well as porch and frame rate control for the new display modes
• Approximate LCD response time emulation (exposed as a user setting)
• Approximate analog gamma emulation (exposed as a user setting), as well as approximated presets
• Configurable LCD internal clock rate in misc debug panel (between 9.5 MHz and 10.5 MHz)
• Digital gamma emulation for red/blue components
• Black/white color parameter for unused lines in partial mode
• Endianness parameter for 16bpp pixel format through SPI
• LCM Control parameter, as well as other parameters that reverse scan direction
• RAM bypass and HV mode for RGB display mode

Fixed behavior:

• Changes to certain display modes and scroll/partial parameters take effect only at the next VSYNC
• VSYNC signal from the PL111 is properly ignored if the current frame hasn't finished yet
• Various PL111 timing fixes, such as sending HSYNC signals during a multi-line VSYNC and properly applying the clock divisor in some places
• Accurate timing for LCD RAM reads during display scanning
• Low bits of color components are filled as configured for 12bpp and 16bpp pixel formats
• Many LCD RAM pointer edge cases are fixed, and support is added for different wrapping modes
• Fixed endianness handling for 16bpp modes on the PL111

Performance improvements:

• Scheduler is rewritten to use 64-bit timestamps with a fixed (least common multiple) clock unit, and event clocks refactored to use multiplication
• LCD scanning now batches pixels, and batches are only processed at the end of each line, before LCD RAM is modified on the current line, or when the inverted mode is changed
• Partial and disabled display modes are checked and rendered only once per line, instead of on each pixel
• Inverted and idle modes, as well as backlight level, are integrated into the gamma lookup and thus reduced to zero cost
• Streamlined the hot path of DMA FIFO to RGB interface to LCD RAM, handling pixel format changes in parallel when possible
• Non-DMA rendering mode also takes advantage of parallelized pixel format changes