You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Copy file name to clipboardExpand all lines: optvm/README.md
+21-11Lines changed: 21 additions & 11 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -13,32 +13,42 @@ a physical machine. Therefore, all our optimization passes will work on the inst
13
13
## Guide
14
14
15
15
*[Register](src/main/java/com/compilerprogramming/ezlang/compiler/Register.java) - implements a virtual register. Virtual registers
16
-
have a name, type, and id - the id is unique, but name is not. Initially the compiler generates unique registers for every local
16
+
have a name, type, id, frameSlot - the id is unique, but the name is not. Initially the compiler generates unique registers for every local
17
17
and temporary, the number of registers grows as we convert to SSA and back out of SSA. Finally, as we run the Chaitin register allocator
18
-
we shrink down the number of virtual registers to the minimum.
18
+
we shrink down the number of virtual registers to the minimum. When executing code, the abstract machine uses the frameSlot as the location
19
+
of the virtual register in the executing function's stack frame. Registers that do not have overlapping lifetimes can share the same
20
+
frameSlot.
19
21
*[RegisterPool](src/main/java/com/compilerprogramming/ezlang/compiler/RegisterPool.java) - simple pool to allow us to find a register
20
22
by its id, and to allocate new virtual registers.
21
23
*[BasicBlock](src/main/java/com/compilerprogramming/ezlang/compiler/BasicBlock.java) - Defines our basic block - which contains instructions
22
-
that execute sequentially. A basic block ends with a branch. There are two distinguished basic blocks in every function: entry and exit.
24
+
that execute sequentially. A basic block ends with a branch. There are two distinguished basic blocks in every function: entry and exit.
23
25
*[BBHelper](src/main/java/com/compilerprogramming/ezlang/compiler/BBHelper.java) - Some utilities that manipulate basic blocks.
24
26
*[Operand](src/main/java/com/compilerprogramming/ezlang/compiler/Operand.java) - Operands in instructions. Both definitions and uses are treated
25
27
as operands. Instruction can have at most one definition; but an instruction can have multiple use operands. Operands can hold registers or
26
28
constants or pointers to basic blocks.
27
-
*[Instruction](src/main/java/com/compilerprogramming/ezlang/compiler/Instruction.java) - Instructions in basic blocks.
29
+
*[Instruction](src/main/java/com/compilerprogramming/ezlang/compiler/Instruction.java) - Instructions - sequential instructions reside in
30
+
basic blocks. Some instructions define variables (registers) and some use them.
28
31
*[DominatorTree](src/main/java/com/compilerprogramming/ezlang/compiler/DominatorTree.java) - Calculates dominator tree and dominance frontiers.
29
-
*[LiveSet](src/main/java/com/compilerprogramming/ezlang/compiler/LiveSet.java) - Bitset used to track liveness of registers.
30
-
*[Liveness](src/main/java/com/compilerprogramming/ezlang/compiler/Liveness.java) - Liveness calculator, works for both SSA and non-SSA forms.
32
+
*[LiveSet](src/main/java/com/compilerprogramming/ezlang/compiler/LiveSet.java) - Bitset used to track liveness of registers. We exploit the fact that
33
+
each register has a unique integer ID and these ids are allocated in a sequential manner.
34
+
*[Liveness](src/main/java/com/compilerprogramming/ezlang/compiler/Liveness.java) - Liveness calculator, works for both SSA and non-SSA forms. Computes
35
+
liveness data per basic block - mainly live-out. Note that the interference graph builder starts here and computes instruction level liveness as necessary.
31
36
*[EnterSSA](src/main/java/com/compilerprogramming/ezlang/compiler/EnterSSA.java) - Transforms into SSA, using algorithm by Preston Briggs.
32
37
*[ExitSSA](src/main/java/com/compilerprogramming/ezlang/compiler/ExitSSA.java) - Exits SSA form, using algorithm by Preston Briggs.
*[LoopNest](src/main/java/com/compilerprogramming/ezlang/compiler/LoopNest.java) - Representation of loop nesting.
38
+
*[LoopFinder](src/main/java/com/compilerprogramming/ezlang/compiler/LoopFinder.java) - Discovers loops. (Not used yet)
39
+
*[LoopNest](src/main/java/com/compilerprogramming/ezlang/compiler/LoopNest.java) - Representation of loop nesting. (Not used yet)
35
40
*[InterferenceGraph](src/main/java/com/compilerprogramming/ezlang/compiler/InterferenceGraph.java) - Representation of an Interference Graph
36
41
required by the register allocator.
37
-
*[InterferenceGraphBuilder](src/main/java/com/compilerprogramming/ezlang/compiler/InterferenceGraphBuilder.java) - Constructs InteferenceGraph for a set
38
-
of basic bocks, using liveness information.
42
+
*[InterferenceGraphBuilder](src/main/java/com/compilerprogramming/ezlang/compiler/InterferenceGraphBuilder.java) - Constructs an InterferenceGraph for a set
43
+
of basic bocks, using basic block level liveness information as a starting point for calculating instruction level liveness.
Chaitin Graph Coloring Register Allocator. Since our target machine here is an abstract machine, we do not really needing spilling support
46
+
as we can size each function's stack frame to accommodate the number of registers needed such that each register is really a slot in the stack
47
+
frame. But we will eventually simulate an abstract machine with a limited set of registers and a separate stack frame.
41
48
42
49
## Compiler
43
50
44
51
*[CompiledFunction](src/main/java/com/compilerprogramming/ezlang/compiler/CompiledFunction.java) - builds and encapsulates the IR for a single function.
52
+
*[Compiler](src/main/java/com/compilerprogramming/ezlang/compiler/Compiler.java) - simple orchestrator of compilation tasks.
53
+
*[Optimizer](src/main/java/com/compilerprogramming/ezlang/compiler/Optimizer.java) - simple orchestrator of optimization steps. Currently
54
+
does not have optimization passes, but translates to SSA and out and then runs the graph coloring register allocator.
0 commit comments