Repository navigation
Zero lab 3
Welcome to this lab in which you will learn how to create a convolutional filter using HLS. For your information, you can use Xilinx's HLS opencv library to produce this kind of IPs which is a greate method if you want to achieve faster design process, however you may find the library a bit "rigid" regarding the choice of interfaces and customizations.
Convolution filter are the core functions that allows image processing, you can find thousands of papers on how to implement it on different plateforms (GPU CPU even on micro controllers) of course will focus on FPGA implementation in our case.
If you are not familliar with the mathematical aspect of convolution filters, stop right there and check out this presentation made by Computerphile youtube channel : https://www.youtube.com/watch?v=C_zFhWdM4ic
In image processing, a convulution filter operation looks like this :
The input array is our image to process, in this composed of 3 lines each of them containing 3 pixels. The kernel will define the mathematical operation to apply, in this case we have a 2 by 2 kernel (most commonly we encounter 3 x 3 or 5 x 5 kernels). The output array is the resulting image after appling the kernel's opertions.
In the concept of convolution, we execute kernel's operation and then "slide" the kernel to the next pixel on the right.
If we reach out the edge of the input image we place the kernel on the first pixel of next line.
For a better pratice before getting your hands on FPGA implementation it's recommended to grab a piece of paper and try to reproduce the example presented above. Correction is available here https://d2l.ai/chapter_convolutional-neural-networks/conv-layer.html
For implementation of this processing we will use "sliding window" architecture presented in this article : https://www.researchgate.net/publication/261672713_Design_space_exploration_for_image_processing_architectures_on_FPGA_targets
lab under contruction