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ltigny edited this page Jan 11, 2023 · 5 revisions

HLS-Zybo wiki

This wiki is created and maintained by Deverne, reader will find

  • a general description of HLS technology, it's pros and cons from both technical and business point of vue
  • a presentation of IP design flow using using Vitis HLS 2020.2
  • a best practice guide

To perform this lab you will need

  • Vitis HLS 2020.2
  • ImageJ
  • ~30 minutes

HLS technology presentation

HLS santds for "High Level Synthesis" and has been developped since 2001 in several silicon lead companies such as Xilinx. Its main goal, from a business point of vue, is to allows gateware design engineers to produce IPs much faster which brings project development cost down to 1/5 of the inital budget (from our experience sometimes to a 1/10 depending on the HLS tool or the considered design to produce).

HLS technologies allows this breakthrough by

  • letting designers to describe IPs using "dataflow paradigm" instead of "register level paradigm" in order reduce the time required to debug synthaxic errors
  • automate, as much as possible, the description of standard interface
  • automate validation procedure and add early bug detection features

There are some common thoughts on HLS tools such as "not ressource efficient", which was true in the past in the case of Vivado design suite, and it will be possible to acheive better ressource optimizations using classical methods (using HDL) however the cost for these optimization gets outragesly higher with HLS tools getting more efficient with continuous releases.

To find out more, take a look at HLS first lab https://github.com/Deverne-labs/HLS-Zybo/wiki/Zero-lab-1

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