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SYMBEX-1 V2.0.0 - Block-Gated Architecture

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@Eden-sudo Eden-sudo released this 04 Sep 00:29
· 70 commits to master since this release
v2.0.0
54e40b3

🚀 SYMBEX-1: Block-Gated 1-Bit Inference Engine (v2.0.0)

SYMBEX-1 v2.0.0 is a massive architectural overhaul, transitioning from static multi-bit slicing to a purely dynamic 1-bit Block-Gated topology. Designed for bare-metal microcontrollers (SRAM < 2 KB), it drops computational latency by orders of magnitude while achieving FP32-level accuracy using strictly binary math (XNOR + Popcount).

✨ Main Features

  • Dynamic Block-Gating (Early Exit): The network now evaluates peripheral data in real-time and physically skips inactive blocks (continue;), evading dead computation cycles.
  • Pure 1-Bit XNOR+Popcount Engine: Complete eradication of 8-bit asymmetric outliers. The processor never multiplies arithmetically.
  • Zero-Heap & Stack-Safe: Maintains a strict static memory architecture. Zero usage of malloc, new, or Variable Length Arrays (VLAs).
  • Modular Compiler Core: The Python compiler was rewritten into a professional compiler_core/ SDK (Trainer, Numpy Simulator, Validator, Exporter) that auto-generates the entire C++ wiring.

🛠️ What's New in this Version

  • [UPDATE] Architectural Leap: Replaced the legacy V1 static Voting Pool with the V2 Block-Gated topology.
  • [NEW] SWAR Algorithm Injection: Implemented SIMD Within A Register (SWAR) emulation via HAL (symbex_config.h) for ultra-fast bit counting on simple microcontrollers lacking native popcount.
  • [NEW] Hardware-Accurate Numpy Simulator: Python now simulates the exact C++ int32_t bit-math (including Insertion Sort Tie-Breaking logic) to guarantee 100.00% fidelity before flashing to the board.
  • [FIX] Flash Memory Optimization: Reduced Flash memory footprint by over 50% (down to ~4.8 KB for a 512-neuron hidden layer) by eliminating the old outlier overhead arrays.
  • [NEW] Clean SDK Examples: Restructured official benchmarks for 01_Bitslice_V1 and 02_BlockGated_V2 directly accessible via the Arduino IDE.

📊 V2 Performance Profile (ESP32 @ 240MHz)

  • Topology: 64 → 512 (1-bit) → 10
  • Accuracy: 95.28% (Surpassing the 94.17% FP32 baseline)
  • Latency: ~645 µs
  • Flash Size: ~4.8 KB
  • Hardware Fidelity: 100.00%
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