MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer #1
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Add SDHCI controller defines, this is useful as the version in the register does not explictly map to a specification version. For example vesion 4.10 of the specification is version 0x04. Change-Id: Ibb718034f0e9719daf0ed9eaafbae947a0ace241 Reviewed-on: https://git-master.nvidia.com/r/1843759 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
Clock control is similar in SDHCI versions greater then version 2. Add support for more recent versions of the controller specification. SD card support for 1.8V is also present in controller versions 3 and greater. Change-Id: Ib3fce116a1f3934db6f78d81d3de20efac0e3cb0 Reviewed-on: https://git-master.nvidia.com/r/1808676 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Add SDHCI controller defines, this is useful as the version in the register does not explictly map to a specification version. For example vesion 4.10 of the specification is version 0x04. Change-Id: Ibb718034f0e9719daf0ed9eaafbae947a0ace241 Reviewed-on: https://git-master.nvidia.com/r/1843759 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com> (cherry picked from commit 61bc3f3) Reviewed-on: https://git-master.nvidia.com/r/1848447
Clock control is similar in SDHCI versions greater then version 2. Add support for more recent versions of the controller specification. SD card support for 1.8V is also present in controller versions 3 and greater. Change-Id: Ib3fce116a1f3934db6f78d81d3de20efac0e3cb0 Reviewed-on: https://git-master.nvidia.com/r/1808676 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850042 Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
This function is exposed by the MemoryAllocationLib header. An AllocateZeroPool() function has been added to fix modules depending on this library and this function. Change-Id: I7f0f6612b070fd4de523f2d79e59ff400e9e41c4 Reviewed-on: https://git-master.nvidia.com/r/1919689 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Expose BaseSortLib for use in SEC and PEI phases. Change-Id: Ibd88c488b9487ac255186a6b6adb883ad21222b2 Reviewed-on: https://git-master.nvidia.com/r/1919690 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Restrict expanded version support to defined versions in the SDHCI specification. Change-Id: I6d7f805967a185d7569b539fcd9155565410d222 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1922891 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Add function to allow enabling and disabling of the clock using the SCMI interface. Update the protocol GUID as the protocol interface has changed. Change-Id: Ibe2ae1e6e091414e5d8290b83ca0ee51384c1b31 Reviewed-on: https://git-master.nvidia.com/r/1933785 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Add capability declaration for V4.x 64 bit system address support. This would be used for host controllers working in version 4. Enable 64 bit DMA support in PCI layer if V3 or V4 64 bit support is enabled in host capability register. The usage of this new field does not need a guard for version check as spec for previous SDMMC versions defines this field as reserved with default value of 0. Change-Id: I0b2d3a27c76767faf01d13776889daf19093b23b Reviewed-on: https://git-master.nvidia.com/r/1939495 Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
If V4 64 bit address mode is enabled in compatibility register, program controller to enable V4 host mode and use appropriate ADMA descriptors supporting 64 bit addresses. Change-Id: Ia6357dbbf706c30107eb101123d8938fab18d01a Reviewed-on: https://git-master.nvidia.com/r/1938654 Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
If host controller version is above V4.0, enable ADMA2 with 26b data length support for better performance. HC 2 register is configured to use 26 bit data lengths and ADMA2 descriptors are configured appropriately. Change-Id: I33290482e8254179d8f1d679964b1cd1827ba5ab Reviewed-on: https://git-master.nvidia.com/r/1941563 Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
SdReadWrite can be called with a NULL Token for synchronous operations. Add guard for DEBUG print to only print event pointer with Token is not NULL. Change-Id: I075ead94b7277a584c6a3c68ee443928a05a1b37 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1945027 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Switch to ZeroMem from SetMem per upstream comments Change-Id: I08802bbdfc0b38776dfa6ade30719ff47a02217e Reviewed-on: https://git-master.nvidia.com/r/1945842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com> Tested-by: Jeff Brasen <jbrasen@nvidia.com>
Updated NULL pointer check per upstream code review and to match what is in Emmc driver. Change-Id: I2ad17425e73d7bbccfcd60b56b37c3f514e28e25 Reviewed-on: https://git-master.nvidia.com/r/1952151 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
Change flash related drivers from being UEFI drivers to DXE drivers. NVIDIA FVB driver needs these drivers to be available early on. Without this change these drivers wait for all architecture protocols to be available before being dispatched. DO NOT UPSTREAM Change-Id: Ic4937ff7fffc701bed20507ad292b98ebc893a18 Reviewed-on: https://git-master.nvidia.com/r/1950960 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1185 SdMmcHcReset used to set all bits of Software Reset Register to 1 including reserved ones, which on some controllers may result in timeout. Now only first bit is set, which means "Software Reset for All". Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Change-Id: I3f9f66842c5b82f567836b2fe37fd85ce2166cfe Reviewed-on: https://git-master.nvidia.com/r/1966949 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Chetan Kumar <chetankumarn@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Add SDMA, ADMA2 and 26b data length support. If V4 64 bit address mode is enabled in compatibility register, program controller to enable V4 host mode and use appropriate SDMA registers supporting 64 bit addresses. If V4 64 bit address mode is enabled in compatibility register, program controller to enable V4 host mode and use appropriate ADMA descriptors supporting 64 bit addresses. If host controller version is above V4.0, enable ADMA2 with 26b data length support for better performance. HC 2 register is configured to use 26 bit data lengths and ADMA2 descriptors are configured appropriately. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Change-Id: I592b72a2e6a87a045c545b6b6f957edf2cb63571 Reviewed-on: https://git-master.nvidia.com/r/1952429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
Needed for VDK which supports 4.10 controller without 26-bit support DO NOT UPSTREAM Change-Id: I2116d3bdd1066b0e13b23699619a0077cdd67348 Reviewed-on: https://git-master.nvidia.com/r/1968182 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Needed on VDK due to errors. DO NOT UPSTREAM Change-Id: I99ddb7ff3a9ad80548c478cd395c1471fd3cef9b Reviewed-on: https://git-master.nvidia.com/r/1968183 Tested-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Change-Id: I1050d083cc3ca311066f4eae6765c794738a47b8
SDCC clock initialization call got removed as part of automerge. Adding it back. DO NOT UPSTREAM Change-Id: Ifbfc8c183b6e89ed56bc3408ddda8547a16a9dc4 Reviewed-on: https://git-master.nvidia.com/r/1973470 Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Mayur Gudmeti <mgudmeti@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Merge edk2 commits till 39699d0 into dev/jbrasen/parker_bringup Change-Id: Id5cff62c6532df516fc3ee0c9c582facd32d1b74
Merge edk2 commits till 15666b8 into dev/jbrasen/parker_bringup Change-Id: Id6a4bd118149ecbf91f992346c7435ff041ab08d
Revert MODULE_TYPE flag for flash related drivers. The objective has been achieved by using the apriory list. DO NOT UPSTREAM Change-Id: I94603b30622340ce750cfd9b2691ba3c3dda9be7 Reviewed-on: https://git-master.nvidia.com/r/1998994 Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jeff Brasen <jbrasen@nvidia.com>
Jira TEGRAUEFI-393 Change-Id: I95ce8b1a9f9fc477f1aa9d0d6824c432c571d662
Merge edk2 commits till 7381bd3 into dev-kernel. Change-Id: I901bdf81b853e68140e6b1dbb5f8330f77ec6a8b
Update the submodule reference to be the merge commit of 1.1.0j due to how gerrit intake on this works. Jira TEGRAUEFI-393 Change-Id: I41ce49ed2a4c1892644b932ecba0d695de1782b9 Reviewed-on: https://git-master.nvidia.com/r/1998005 Tested-by: Jeff Brasen <jbrasen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Change-Id: Ia756ed32e59b24d972d88703f4af6ca07b0cb65f
Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register accesses from being split up into 8-bit accesses. Change-Id: I009d25bda6a63ffb21225edd3bbe6158d868e7c0 Reviewed-on: https://git-master.nvidia.com/r/2004038 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Change-Id: I215dc3f7905e090e3b1e87a364996290c3143f87
Change-Id: I50b0f34b2c2e672324bf4b42eca5248170bbe1dc Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2538171 GVS: Gerrit_Virtual_Submit Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Change-Id: Id983dc72fcf85c117607dd117d78bba58e581741
Remove duplicate libfdt.h include statement in AndroidBootImgLib Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Change-Id: I4a6978811ed079a4e5d2fc108046b49cfcf94acb Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2593744 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Update AndroidBootImgBoot to use a single return point Make sure Kernel args are freed and Image is unloaded. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Change-Id: I4f203fb7a91967bdf0cc5ff454bce091618fce5e Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2593745 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Currently if mAndroidBootImg->UpdateDtb is not supported on the platform the device tree updates of the initrd are not made. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Change-Id: I443dde4c23dafbd285c7d3b227461c476e684ccc Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2593746 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Add support under a pcd feature for using the new interface to pass initrd to the linux kernel instead of via device tree. This feature is also enabled if ACPI tables are present, and will skip locating and installation of device tree. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Change-Id: Ie2568170801205fa623f862da49ae178121d181f Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2586736 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Currently, at ExitBootServices() time, the GICv3 driver signals
End-Of-Interrupt (EOI) on all interrupt lines that are supported by the
interrupt controller. This appears to have been carried over from the
GICv2 version, but has been turned into something that violates the GIC
spec, and may trigger SError exceptions on some implementations.
Marc puts it as follows:
The GIC interrupt state machine is pretty strict. An interrupt can
only be deactivated (with or without prior priority drop) if it has
been acknowledged first. In GIC speak, this means that only the
following sequences are valid:
With EOImode==0:
x = ICC_IAR{0,1}_EL1;
ICC_EOIR{0,1}_EL1 = x;
With EOImode==1:
x = ICC_IAR{0,1}_EL1;
ICC_EOIR{0,1}_EL1 = x;
ICC_DIR_EL1 = x;
Any write to ICC_EOIR{0,1}_EL1 that isn't the direct consequence of
the same value being read from ICC_IAR{0,1}_EL1, and with the correct
nesting, breaks the state machine and leads to unpredictable results
that affects *all* interrupts in the system (most likely, the priority
system is dead). See Figure 4-3 ("Interrupt handling state machine")
in Arm IHI 0069F for a description of the acceptable transitions.
Additionally, on implementations that have ICC_CTLR_EL1.SEIS==1, a
SError may be generated to signal the error. See the various
<quote>
IMPLEMENTATION_DEFINED "SError ....";
</quote>
that are all over the pseudocode contained in the same architecture
spec. Needless to say, this is pretty final for any SW that would do
silly things on such implementations (which do exist).
Given that in our implementation, every signalled interrupt is acked,
handled and EOId in sequence, there is no reason to EOI all interrupts
at ExitBootServices() time in the first place, so let's just drop this
code. This fixes an issue reported by Marc where an SError is triggered
by this code, bringing down the system.
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Change-Id: I79ada7cf6074e204883ec140826862f49c43d130
Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2607341
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Ashish Singhal <ashishsingha@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Increase TPL to TPL_NOTIFY to allow for use if caller is > TPL_CALLBACK. This allows services like variable services that run at TPL_NOTIFY to be hosted on ScsiDisks (i.e. UFS) Change-Id: I793da97eba8e04b1308e3d7b7287c88f9187868f Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2635887 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Jeff Brasen <jbrasen@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Change-Id: Idd6773e22218b513aa88e1f8d37caf01085f11a9
MMU is not treating device memory properly in some situations. Add memory fence while accessing MMIO memory to get around this issue while it is under debug with the HW team. Change-Id: I10cfd845916815716d2115bdfb77737fae5c5b27 Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2646460 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-sw-mobile-l4t <svc-sw-mobile-l4t@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit 94075f9121b4e01e224c083179475a04ee233e73) Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2654278
Typically, the information of the SMBIOS type 1/2/3 is fetched from an FRU device during UEFI booting intead of fixed PCDs. Therefore, this patch is to add more HII string fields in the OemMiscLib and support updating these SMBIOS types with the strings provided by the OemMiscLib if the PCDs are empty. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Change-Id: Ic9d6da5c92d100a5d86fc28435629743d898a200 (cherry picked from commit ad0c9127bbdae7f6167333696c1716c57fb074a4) Change-Id: Iad078f34024c7e93d8a6dd5c0f5784f329d659ed Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2659464 Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> GVS: Gerrit_Virtual_Submit
This patch removes duplicate HII string definition in the MiscSystemManufacturer.uni. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Change-Id: If7f3e506cdd734c7751066352726a0d9dbdfe65d (cherry picked from commit 706493db4da9a73202e7f4394fe4cc0f8b94a4da) Change-Id: I86d4aae10067e235e3151a1c861b439d9b830685 Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2659462 Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> GVS: Gerrit_Virtual_Submit
Currently, the serial and part number of a processor are filled with fixed PCDs. However, they may be updated dynamically according to the information being passed from a the pre-UEFI firmware during booting. So, this patch is to support updating these string fields from OemMiscLib if the PCDs are empty. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Change-Id: I594ea99c172e9c76ba009db7a8fd69871dea4840 (cherry picked from commit 2eb837e2099afddb3573b8cef5ae8920a02dd619) Change-Id: Id66fe292b78ca5105b3e37427fec1848803d4334 Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2659519 Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> GVS: Gerrit_Virtual_Submit
Add support for partial free of non cached buffers. If a request for less than the full size is requested new allocations for the remaining head and tail of the buffer are added to the list. Added verification that Buffer is EFI_PAGE_SIZE aligned. The XHCI driver does this if the page size for the controller is >4KB. Change-Id: Icaf54ce56878d550bbeda88b714bc15781422eac Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2684950 Tested-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> GVS: Gerrit_Virtual_Submit
This was referenced Apr 11, 2022
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Included in edk2-stable202208-134-g6a2b20ff97 |
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Nov 10, 2023
Root cause: 1. Before DisableReadonlyPageWriteProtect() is called, the return address (#1) is pushed in shadow stack. 2. CET is disabled. 3. DisableReadonlyPageWriteProtect() returns to #1. 4. Page table is modified. 5. EnableReadonlyPageWriteProtect() is called, but the return address (#2) is not pushed in shadow stack. 6. CET is enabled. 7. EnableReadonlyPageWriteProtect() returns to #2. #CP exception happens because the actual return address (#2) doesn't match the return address stored in shadow stack (#1). Analysis: Shadow stack will stop update after CET disable (DisableCet() in DisableReadOnlyPageWriteProtect), but normal smi stack will be continue updated with the function called and return (DisableReadOnlyPageWriteProtect & EnableReadOnlyPageWriteProtect), thus leading stack mismatch after CET re-enabled (EnableCet() in EnableReadOnlyPageWriteProtect). According SDM Vol 3, 6.15-Control Protection Exception: Normal smi stack and shadow stack must be matched when CET enable, otherwise CP Exception will happen, which is caused by a near RET instruction. CET is disabled in DisableCet(), while can be enabled in EnableCet(). This way won't cause the problem because they are implemented in a way that return address of DisableCet() is poped out from shadow stack (Incsspq performs a pop to increases the shadow stack) and EnableCet() doesn't use "RET" but "JMP" to return to caller. So calling EnableCet() and DisableCet() doesn't have the same issue as calling DisableReadonlyPageWriteProtect() and EnableReadonlyPageWriteProtect(). With above root cause & analysis, define below 2 macros instead of functions for WP & CET operation: WRITE_UNPROTECT_RO_PAGES (Wp, Cet) WRITE_PROTECT_RO_PAGES (Wp, Cet) Because DisableCet() & EnableCet() must be in the same function to avoid shadow stack and normal SMI stack mismatch. Note: WRITE_UNPROTECT_RO_PAGES () must be called pair with WRITE_PROTECT_RO_PAGES () in same function. Change-Id: I4e126697efcd8dbfb4887da034d8691bfca969e3 Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4534 Bug Details: PixieFail Bug #1 CVE-2023-45229 CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N CWE-125 Out-of-bounds Read Change Overview: Introduce Dhcp6SeekInnerOptionSafe which performs checks before seeking the Inner Option from a DHCP6 Option. > > EFI_STATUS > Dhcp6SeekInnerOptionSafe ( > IN UINT16 IaType, > IN UINT8 *Option, > IN UINT32 OptionLen, > OUT UINT8 **IaInnerOpt, > OUT UINT16 *IaInnerLen > ); > Lots of code cleanup to improve code readability. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
jgarver
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4534 PixieFail Bug #1 CVE-2023-45229 CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N CWE-125 Out-of-bounds Read Change Overview: Introduce Dhcp6SeekInnerOptionSafe which performs checks before seeking the Inner Option from a DHCP6 Option. > > EFI_STATUS > Dhcp6SeekInnerOptionSafe ( > IN UINT16 IaType, > IN UINT8 *Option, > IN UINT32 OptionLen, > OUT UINT8 **IaInnerOpt, > OUT UINT16 *IaInnerLen > ); > Lots of code cleanup to improve code readability. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com> Tested-by: Jeff Brasen <jbrasen@nvidia.com>
jgarver
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4534 Bug Details: PixieFail Bug #1 CVE-2023-45229 CVSS 6.5 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N CWE-125 Out-of-bounds Read Change Overview: Introduce Dhcp6SeekInnerOptionSafe which performs checks before seeking the Inner Option from a DHCP6 Option. > > EFI_STATUS > Dhcp6SeekInnerOptionSafe ( > IN UINT16 IaType, > IN UINT8 *Option, > IN UINT32 OptionLen, > OUT UINT8 **IaInnerOpt, > OUT UINT16 *IaInnerLen > ); > Lots of code cleanup to improve code readability. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com> Reviewed-by: Jeff Brasen <jbrasen@nvidia.com> Tested-by: Jeff Brasen <jbrasen@nvidia.com>
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Add support for partial free of non cached buffers.
If a request for less than the full size is requested new allocations
for the remaining head and tail of the buffer are added to the list.
Added verification that Buffer is EFI_PAGE_SIZE aligned.
The XHCI driver does this if the page size for the controller is >4KB.
Change-Id: Icaf54ce56878d550bbeda88b714bc15781422eac
Signed-off-by: Jeff Brasen jbrasen@nvidia.com
Reviewed-on: https://git-master.nvidia.com/r/c/3rdparty/edk2/+/2684950
Tested-by: Ashish Singhal ashishsingha@nvidia.com
Reviewed-by: Ashish Singhal ashishsingha@nvidia.com
Reviewed-by: svcacv svcacv@nvidia.com
GVS: Gerrit_Virtual_Submit