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RegisterMap
Contains descriptions of registers and how to use them.
| Register name | Register description |
| Device ID registers | |
| DEVICE_ID_REG | If defined in a project contains an ID for the design currently running on the board. |
| DEVICE_REVISION_REG | Revision number. |
| DEVICE_STR_REG | Can be read continuosuly to give a string identifying the running project |
| MAC queues registers | registers for the MAC Rx and Tx queues. |
| MAC_GRP_X_CONTROL_REG | Contains bits that can be used to change the state of the MAC queues. See MAC Control Bits. |
| RX_QUEUE_X_NUM_PKTS_STORED_REG | Counts the total number of pkts that have went into the Rx Queue. |
| RX_QUEUE_X_NUM_PKTS_DROPPED_FULL_REG | Counts the number of pkts that have been dropped because the Rx queue is full. |
| RX_QUEUE_X_NUM_PKTS_DROPPED_BAD_REG | Counts the number of pkts dropped because of CRC failure. |
| RX_QUEUE_X_NUM_WORDS_PUSHED_REG | Counts the number of 64-bit words that have been sent into the user data path from this Rx queue. |
| RX_QUEUE_X_NUM_BYTES_PUSHED_REG | Counts the number of bytes that have been sent into the user data path from this Rx queue. |
| RX_QUEUE_X_NUM_PKTS_DEQUEUED_REG | Counts the number of packets that have been removed from the Rx queue and pushed into the Rx queue. |
| RX_QUEUE_X_NUM_PKTS_IN_QUEUE_REG | Gives the number of packets that are currently waiting in the Rx queue. |
| TX_QUEUE_X_NUM_PKTS_IN_QUEUE_REG | Gives the number of packets that are currently waiting in the Tx queue to be sent out to the Ethernet. |
| TX_QUEUE_X_NUM_PKTS_SENT_REG | Gives the number of packets that have been sent out to the Ethernet. |
| TX_QUEUE_X_NUM_WORDS_PUSHED_REG | Gives the number of words sent out to the Ethernet. |
| TX_QUEUE_X_NUM_BYTES_PUSHED_REG | Gives the number of bytes that have been sent out of the Tx queue to the Ethernet. |
| TX_QUEUE_X_NUM_PKTS_ENQUEUED_REG | Gives the number of packets that have ever went into the Tx queue to be sent out to the Ethernet. |
| CPU register queue registers | These are only available if using the CPU register queues which are not in any the reference designs. They can be added by very advanced users who wish to add more CPU queues in addition to the available 4 regular CPU DMA queues. See CPU Register Queues for information on using these queues. |
| CPU_REG_Q_X_WR_DATA_WORD_REG | Writing into this register writes a 32-bit word into the CPU Rx Queue. |
| CPU_REG_Q_X_WR_CTRL_WORD_REG | Writing into this register specifies which ctrl word goes with the data word. |
| CPU_REG_Q_X_WR_NUM_WORDS_LEFT_REG | Gives the space left in the Rx queue. |
| CPU_REG_Q_X_WR_NUM_PKTS_IN_Q_REG | Gives the number of packets that are waiting to be pushed into the user data path from this queue. |
| CPU_REG_Q_X_RD_DATA_WORD_REG | Reading from this register will read a single word from the register CPU Tx queue. |
| CPU_REG_Q_X_RD_CTRL_WORD_REG | Reading from this register will read the ctrl word associated with the last word read. |
| CPU_REG_Q_X_RD_NUM_WORDS_AVAIL_REG | This register gives the total number of 32-bit words available to read. |
| CPU_REG_Q_X_RD_NUM_PKTS_IN_Q_REG | Gives the number of packets that are stored in the CPU Tx queue to be read by the CPU. |
| CPU_REG_Q_X_RX_NUM_PKTS_RCVD_REG | Counts the number of packets that have arrived from the CPU and been sent into the user data path. |
| CPU_REG_Q_X_TX_NUM_PKTS_SENT_REG | Counts the number of packets sent out of the user data path and read by the CPU |
| CPU_REG_Q_X_RX_NUM_WORDS_RCVD_REG | Counts the number of words that have arrived from the CPU and been sent into the user data path. |
| CPU_REG_Q_X_TX_NUM_WORDS_SENT_REG | Counts the number of words sent out of the user data path and read by the CPU |
| CPU_REG_Q_X_RX_NUM_BYTES_RCVD_REG | Counts the number of bytes that have arrived from the CPU and been sent into the user data path. |
| CPU_REG_Q_X_TX_NUM_BYTES_SENT_REG | Counts the number of bytes sent out of the user data path and read by the CPU |
| DMA registers | Used internally |
| DMA_TX_QUE_X_REG | Used for DMA |
| DMA_TX_QUE_X_LAST_1_BYTE_REG | Used for DMA |
| DMA_TX_QUE_X_LAST_2_BYTE_REG | Used for DMA |
| DMA_TX_QUE_X_LAST_3_BYTE_REG | Used for DMA |
| DMA_TX_QUE_X_LAST_4_BYTE_REG | Used for DMA |
| MDIO registers | The MDIO registers map the PHY registers to memory so that they can be accessed as any other register. Note you need at least 10us between each access for correct functionality. |
| MDIO_X_CONTROL_REG | See MDIO Bits. |
| MDIO_X_STATUS_REG | See MDIO Bits. |
| MDIO_X_PHY_ID_0_REG | See MDIO Bits. |
| MDIO_X_PHY_ID_1_REG | See MDIO Bits. |
| MDIO_X_AUTONEGOTIATION_ADVERT_REG | See MDIO Bits. |
| MDIO_X_AUTONEG_LINK_PARTNER_BASE_PAGE_ABILITY_REG | See MDIO Bits. |
| MDIO_X_AUTONEG_EXPANSION_REG | See MDIO Bits. |
| MDIO_X_AUTONEG_NEXT_PAGE_TX_REG | See MDIO Bits. |
| MDIO_X_AUTONEG_LINK_PARTNER_RCVD_NEXT_PAGE_REG | See MDIO Bits. |
| MDIO_X_MASTER_SLAVE_CTRL_REG | See MDIO Bits. |
| MDIO_X_MASTER_SLAVE_STATUS_REG | See MDIO Bits. |
| MDIO_X_PSE_CTRL_REG | See MDIO Bits. |
| MDIO_X_PSE_STATUS_REG | See MDIO Bits. |
| MDIO_X_MMD_ACCESS_CTRL_REG | See MDIO Bits. |
| MDIO_X_MMD_ACCESS_STATUS_REG | See MDIO Bits. |
| MDIO_X_EXTENDED_STATUS_REG | See MDIO Bits. |
| Input Arbiter Registers | These can be very useful for debugging. |
| IN_ARB_NUM_PKTS_SENT_REG | Gives the number of packets that have been serviced by the input arbiter |
| IN_ARB_LAST_PKT_WORD_0_LO_REG | Gives the least significant 32 bits of the first 64-bit word of the last packet that has passed through the input arbiter. |
| IN_ARB_LAST_PKT_WORD_0_HI_REG | Gives the most significant 32 bits of the first 64-bit word of the last packet that has passed through the input arbiter. |
| IN_ARB_LAST_PKT_CTRL_0_REG | Gives the first 8-bit ctrl word of the last packet that has passed through the input arbiter. |
| IN_ARB_LAST_PKT_WORD_1_LO_REG | Gives the least significant 32 bits of the second 64-bit word of the last packet that has passed through the input arbiter. |
| IN_ARB_LAST_PKT_WORD_1_HI_REG | Gives the most significant 32 bits of the second 64-bit word of the last packet that has passed through the input arbiter. |
| IN_ARB_LAST_PKT_CTRL_1_REG | Gives the second 8-bit ctrl word of the last packet that has passed through the input arbiter. |
| IN_ARB_STATE_REG | Gives the current state of the input arbiter in the state machine. |
| Switch Output Port Lookup module registers | These registers (except for the num hits/misses) are accessed in the same way a table is accessed. See Reading/Writing Tables. |
| SWITCH_OP_LUT_PORTS_MAC_HI_REG | If the most significant bit is cleared, then this entry can be updated by the learning mechanism in the switch. If it is set then the switch will not update this entry. bits 30-16 are the one-hot-encoded ports corresponding to the output ports of a packet with the destination MAC address specified in the entry. bits 15-0 are the 16 most significant bits of the MAC. |
| SWITCH_OP_LUT_MAC_LO_REG | Least significant 32 bits of the MAC address |
| SWITCH_OP_LUT_MAC_LUT_RD_ADDR_REG | Register to write the index of the entry to be read. A write here will update the data registers with the entry's values |
| SWITCH_OP_LUT_MAC_LUT_WR_ADDR_REG | A write into the address will move the data in the data registers to the MAC table entry specified by the write. |
| SWITCH_OP_LUT_NUM_HITS_REG | Gives the number of hits when looking up in the MAC table |
| SWITCH_OP_LUT_NUM_MISSES_REG | Gives the number of misses when looking up in the MAC table |
| Router Output Port Lookup Registers | These define registers for accessing the hardware ARP cache, the Routing Table, setting IP and MAC addresses, statistics,... See Tables in the Router. |
| ROUTER_RT_SIZE | This is not a register but a constant specifying the size of the routing table. |
| ROUTER_ARP_SIZE | This is not a register but a constant specifying the size of the ARP cache. |
| ROUTER_DST_IP_FILTER_TABLE_DEPTH | This is not a register but a constant specifying the size of the IP destination filter table. |
| Router ARP cache registers | See Reading/Writing Tables. |
| ROUTER_OP_LUT_ARP_MAC_HI_REG | High 16 bits of the next hop MAC address in the ARP table |
| ROUTER_OP_LUT_ARP_MAC_LO_REG | Low 32 bits of the next hop MAC address in the ARP table |
| ROUTER_OP_LUT_ARP_NEXT_HOP_IP_REG | Next hop's IP address (set to 0 to match the destination address) |
| ROUTER_OP_LUT_ARP_LUT_RD_ADDR_REG | Write the index of the entry to read from in the ARP table |
| ROUTER_OP_LUT_ARP_LUT_WR_ADDR_REG | Write the index of the entry to write to in the ARP table |
| Routing table registers | See Reading/Writing Tables. |
| ROUTER_OP_LUT_RT_IP_REG | Subnet IP address to match in the Routing table |
| ROUTER_OP_LUT_RT_MASK_REG | Subnet Mask in the router table |
| ROUTER_OP_LUT_RT_NEXT_HOP_IP_REG | Next Hop IP in the router table |
| ROUTER_OP_LUT_RT_OUTPUT_PORT_REG | One-hot-encoded output port in the routing table. |
| ROUTER_OP_LUT_RT_LUT_RD_ADDR_REG | Write the index of the entry to read from in the Routing table |
| ROUTER_OP_LUT_RT_LUT_WR_ADDR_REG | Write the index of the entry to write to in the Routing table |
| Router MAC addresses | NOT a table |
| ROUTER_OP_LUT_MAC_0_HI_REG | high 16 bits of port 0's MAC address |
| ROUTER_OP_LUT_MAC_0_LO_REG | low 32 bits of port 0's MAC address |
| ROUTER_OP_LUT_MAC_1_HI_REG | high 16 bits of port 1's MAC address |
| ROUTER_OP_LUT_MAC_1_LO_REG | low 32 bits of port 1's MAC address |
| ROUTER_OP_LUT_MAC_2_HI_REG | high 16 bits of port 2's MAC address |
| ROUTER_OP_LUT_MAC_2_LO_REG | low 32 bits of port 2's MAC address |
| ROUTER_OP_LUT_MAC_3_HI_REG | high 16 bits of port 3's MAC address |
| ROUTER_OP_LUT_MAC_3_LO_REG | low 32 bits of port 3's MAC address |
| Router IP destination filter table | See Reading/Writing Tables. |
| ROUTER_OP_LUT_DST_IP_FILTER_IP_REG | Destination IP address to filter out and send to the CPU in the Destination IP Filter table |
| ROUTER_OP_LUT_DST_IP_FILTER_RD_ADDR_REG | Index for reading into the destination IP filter table |
| ROUTER_OP_LUT_DST_IP_FILTER_WR_ADDR_REG | Index for writing into the destination IP filter table |
| Router Statistics | |
| ROUTER_OP_LUT_ARP_NUM_MISSES_REG | Total number of misses in the LPM table |
| ROUTER_OP_LUT_LPM_NUM_MISSES_REG | Total number of misses in the ARP table |
| ROUTER_OP_LUT_NUM_CPU_PKTS_SENT_REG | Total number of packets sent from the CPU |
| ROUTER_OP_LUT_NUM_BAD_OPTS_VER_REG | Total number of pkts sent to the CPU because they have IP options or the IP version is not 4 |
| ROUTER_OP_LUT_NUM_BAD_CHKSUMS_REG | Total number of packets dropped because of a checksum failure |
| ROUTER_OP_LUT_NUM_BAD_TTLS_REG | Total number of packets sent to the CPU because the IP TTL field is 0 or 1 |
| ROUTER_OP_LUT_NUM_NON_IP_RCVD_REG | Total number of non-ip packets sent to the CPU (including ARP) |
| ROUTER_OP_LUT_NUM_PKTS_FORWARDED_REG | Total number of packets that have been forwarded by the hardware |
| ROUTER_OP_LUT_NUM_WRONG_DEST_REG | Total number of packets dropped because the destination MAC address was neither a broadcast nor the port's address |
| ROUTER_OP_LUT_NUM_FILTERED_PKTS_REG | Total number of packets sent to the CPU because the destination IP matched an IP in the Destination IP filter table |
| Output Queues registers | |
| OQ_NUM_WORDS_LEFT_REG_X | Gives the space left in the queue in 64-bit words |
| OQ_NUM_PKT_BYTES_STORED_REG_X | Gives the total number of packet bytes stored in the queue |
| OQ_NUM_OVERHEAD_BYTES_STORED_REG_X | Gives the total number of bytes stored in the queue used by module headers |
| OQ_NUM_PKTS_STORED_REG_X | Gives the total number of packets ever stored in the queue |
| OQ_NUM_PKTS_DROPPED_REG_X | Gives the total number of packets dropped from the queue because the queue was full on arrival |
| OQ_NUM_PKT_BYTES_REMOVED_REG_X | Gives the total number of bytes sent from the queue |
| OQ_NUM_OVERHEAD_BYTES_REMOVED_REG_X | Gives the total number of overhead (module header) bytes sent from the queue |
| OQ_NUM_PKTS_REMOVED_REG_X | Gives the total number of packets sent from the queue |
| OQ_ADDRESS_HI_REG_X | Gives/sets the high address of the circular buffer in memory. After changing this register or the OQ_ADDRESS_LO_REG_X you need to reinitialize the queue. See Output Queue Control Bits. |
| OQ_ADDRESS_LO_REG_X | Gives/sets the low address of the circular buffer in memory |
| OQ_WR_ADDRESS_REG_X | The current write pointer |
| OQ_RD_ADDRESS_REG_X | The current read pointer |
| OQ_NUM_PKTS_IN_Q_REG_X | Number of packets currently in the queue waiting to be serviced |
| OQ_MAX_PKTS_IN_Q_REG_X | Used to limit the number of packets that can be in the queue at any given time |
| OQ_FULL_THRESH_REG_X | Used to limit the number of words used from the queue. |
| OQ_NUM_WORDS_IN_Q_REG_X | Gives the number of words currently waiting in the queue. |
| OQ_CONTROL_REG_X | Control register for the output queue. See Output Queue Control Bits. |
| Event capture registers | Only enabled if the event capture module is being used (in the router_buffer_sizing project for example). |
| EVT_CAP_ENABLE_CAPTURE_REG | Write 1 to the register to enable monitoring events. |
| EVT_CAP_SEND_PKT_REG | Write 1 to the register to force the module to send whatever events are stored. |
| EVT_CAP_DST_MAC_HI_REG | Sets the high 16-bits of the destination MAC address of event packets. |
| EVT_CAP_DST_MAC_LO_REG | Sets the low 32-bits of the destination MAC address of event packets. |
| EVT_CAP_SRC_MAC_HI_REG | Sets the high 16-bits of the source MAC address of event packets. |
| EVT_CAP_SRC_MAC_LO_REG | Sets the low 32-bits of the source MAC address of event packets. |
| EVT_CAP_ETHERTYPE_REG | Sets the Ethertype of event packets. |
| EVT_CAP_IP_DST_REG | Sets the IP destination address of event packets. |
| EVT_CAP_IP_SRC_REG | Sets the IP source address of event packets. |
| EVT_CAP_UDP_SRC_PORT_REG | Sets the UDP source port of event packets. |
| EVT_CAP_UDP_DST_PORT_REG | Sets the UDP destination port of event packets. |
| EVT_CAP_OUTPUT_PORTS_REG | Sets the output ports of the event packets. This is a bitmap of the user data path ports to send on. Bit 0 means send out of MAC port 0, bit 1 means send out of nf2c0, bit 2 means send out of MAC port 1, ... See the Guide. |
| EVT_CAP_RESET_TIMERS_REG | Writing a one into the register clears the timers. It is not automatically reset. |
| EVT_CAP_MONITOR_MASK_REG | The is a bitmask specifying which events to monitor. For buffer sizing, 0x7 means monitor stores, removes, and drops. |
| EVT_CAP_TIMER_RESOLUTION_REG | This sets the timer resolution by 2^reg_value. |
| EVT_CAP_NUM_EVT_PKTS_SENT_REG | Gives the total number of event packets sent so far. |
| EVT_CAP_NUM_EVTS_SENT_REG | Gives the total number of events sent so far. |
| EVT_CAP_NUM_EVTS_DROPPED_REG | Gives the total number of events that we couldn't capture. |
| EVT_CAP_SIGNAL_ID_MASK_REG | Bitmask of the signal IDs to monitor. For buffer sizing this is a bitmask of the output queues to monitor. |
| Bit | Bit description |
| TX_QUEUE_DISABLE_BIT_NUM | Setting this bit to one disables sending any packets to the MAC. |
| RX_QUEUE_DISABLE_BIT_NUM | Setting this bit to one disables sending any packets the user data path. |
| RESET_MAC_BIT_NUM | Setting this bit to one resets the MAC queues and core. |
| MAC_DISABLE_TX_BIT_NUM | Setting this bit to one prevents the MAC from sending any packets to the Ethernet. |
| MAC_DISABLE_RX_BIT_NUM | Setting this bit to one prevents the MAC from receiving any packets. |
| MAC_DIS_JUMBO_TX_BIT_NUM | Setting this bit to one causes the MAC to drop any Jumbo packets being sent. |
| MAC_DIS_JUMBO_RX_BIT_NUM | Setting this bit to one causes the MAC to drop any Jumbo packets received. |
| MAC_DIS_CRC_CHECK | Setting this bit to one causes the MAC to ignore checking the CRC on packets. |
| MAC_DIS_CRC_GEN | Setting this bit to one disable CRC generation by the MAC. |
WARNING : These are only used in non-reference designs. All reference designs use DMA queues. Read this section only if you are interested in adding more queues between the host CPU and the NetFPGA.
All packet data sent and received from the CPU queues is in network byte order (only data read from CPU_REG_Q_i_(DATA || CTRL)_WORD_REG) All data is 64-bit aligned. To send a packet to a specific port, the CPU writes the data to the register cpu_port corresponding to that port. So to send data out through port 1, the software should write the packet to CPU queue 1. And data received on CPU Rx queue 1 corresponds to data arriving from MAC port 1.
To write a packet, the software just writes the data to the WR_DATA_WORD_REG address corresponding to the port the software wishes to send the packet on. Each data word has a ctrl word associated with it. CTRL_WORD_REG should be set to 0 for all packet words except the last words where there is one bit set in the CTRL_WORD indicating the position of the last valid byte (1->byte 0 is valid, 2->bytes0,1 valid, 4->bytes 0,1,2 valid, 8->all bytes vld)
Note if a,b,c are the last three bytes of a packet and c is the last byte, the last word should be: x c b a, and the ctrl word should be 0b0100=4
In addition, to maintain 64-bit word alignment, the software needs to always write an even number of words .
For example, to write a packet that has 17 words to send to port 3, and the last word has 1 valid byte (total=65 bytes) 1- Write 0 to CPU_REG_Q_3_WR_CTRL_WORD_REG 2-17: Write the full pkt data words (in network byte order) to CPU_REG_Q_3_WR_DATA_WORD_REG 18- Write 1 to CPU_REG_Q_3_WR_CTRL_WORD_REG -> only the first byte is valid 19- Write the last word to CPU_REG_Q_3_WR_DATA_WORD_REG 20- Write 0 to CPU_REG_Q_3_WR_CTRL_WORD_REG (write one more word to make the total even) 21- Write 0 to CPU_REG_Q_3_WR_DATA_WORD_REG
CPU_REG_Q_3_WR_NUM_WORDS_LEFT will give the number of words left (i.e. space) to write.
For reads, CPU_REG_Q_i_RD_NUM_WORDS_AVAIL will give the number of words available. With every read from CPU_REG_Q_i_RD_DATA_WORD_REG, CPU_REG_Q_i_RD_CTRL_WORD_REG will be set to indicate the last valid byte of the packet. The software should check this register to see if a packet has been fully transferred. Reads are also done in pairs . To perform a read of 65 bytes:
1-16: Read from CPU_REG_Q_i_RD_DATA_WORD_REG then from CPU_REG_Q_i_RD_CTRL_WORD_REG 17- Read from CPU_REG_Q_i_RD_DATA_WORD_REG 18- Read from CPU_REG_Q_i_RD_CTRL_WORD_REG should return 1 indicating only first byte valid 19 Read from CPU_REG_Q_i_RD_DATA_WORD_REG (read one more word to make the total even) 20- Read from CPU_REG_Q_i_RD_CTRL_WORD_REG (Discard the last data read and ctrl read b/c they are padding)
WARNING : The minimum packet size defined by Ethernet is 60 bytes. If you write anything smaller than that, the the hardware will mess up and will stop working correctly.
MDIO registers are hardwired to PHY registers. They map Broadcom's chip functionality to the particular memory addresses, so that PHY's status and control registers can be easily accessible. Access to the particular bits is possible thanks to those register bit offsets.
These are bits in MDIO_X_CONTROL_REG.
| Bit |
| PHY_RST_BIT_POS |
| PHY_LOOPBACK_BIT_POS |
| PHY_SPEED_SEL_LO_BIT_POS |
| PHY_AUTONEG_ENABLE_BIT_POS |
| PHY_PWR_DOWN_BIT_POS |
| PHY_ISOLATE_BIT_POS |
| PHY_RESTART_AUTONEG_BIT_POS |
| PHY_DUPLEX_MODE_BIT_POS |
| PHY_COLLISION_TEST_BIT_POS |
| PHY_SPEED_SEL_HI_BIT_POS |
| PHY_UNIDIR_ENABLE_BIT_POS |
These are bits in MDIO_X_STATUS_REG.
| Bit |
| PHY_100BASE_T4_BIT_POS |
| PHY_100BASE_X_FULL_DPLX_BIT_POS |
| PHY_100BASE_X_HALF_DPLX_BIT_POS |
| PHY_10MBPS_FULL_DPLX_BIT_POS |
| PHY_10MBPS_HALF_DPLX_BIT_POS |
| PHY_100BASE_T2_FULL_DPLX_BIT_POS |
| PHY_100BASE_T2_HALF_DPLX_BIT_POS |
| PHY_EXTENDED_STATUS_BIT_POS |
| PHY_UNIDIR_ABILITY_BIT_POS |
| PHY_MF_PREAMBLE_SPRSN_BIT_POS |
| PHY_AUTONEG_COMPLETE_BIT_POS |
| PHY_REMOTE_FAULT_BIT_POS |
| PHY_AUTONEG_ABILITY_BIT_POS |
| PHY_LINK_STATUS_BIT_POS |
| PHY_JABBER_DETECT_BIT_POS |
| PHY_EXTENDED_CAPABILITY_BIT_POS |
Please note that those offsets can be useful only for NetFPGA utilities needing to access the PHY's state in a portable manner. However, if you plan to couple NetFPGA with other publicly accessible software, consider using macros for MII operations that already may exist on your chosen platform. Most of the open-source operating systems already have MII layer implemented. Notable implementations include:
FreeBSD miibus(4) driver: http://fxr.watson.org/fxr/source/dev/mii/mii.h
Linux MII support: http://fxr.watson.org/fxr/source/include/linux/mii.h?v=linux-2.6
Those files give more detailed information on meaning of particular registers as well. See the Broadcom PHY data sheet for more info.
To read a table:
- Write the index of the entry to read
- Read the data
- Write the data to be stored
- Write the index of the entry to be written
For example: to write an entry into the switch MAC table: index 3, MAC address aa:bb:cc:dd:ee:ff -> MAC port 2
- Write ((0x10<<16) || 0xaabb) into SWITCH_OP_LUT_PORTS_MAC_HI_REG (see below for details)
- Write 0xccddeeff into SWITCH_OP_LUT_MAC_LO_REG
- Write 3 into SWITCH_OP_LUT_MAC_LUT_WR_ADDR_REG
- Write 4 into SWITCH_OP_LUT_MAC_LUT_RD_ADDR_REG
- Read SWITCH_OP_LUT_PORTS_MAC_HI_REG and SWITCH_OP_LUT_MAC_LO_REG
There are three tables in the Router: The ARP table, the Routing table, and the Destination IP filter table.
The ARP table has the following data registers: ROUTER_OP_LUT_ARP_MAC_HI_REG, ROUTER_OP_LUT_ARP_MAC_LO_REG, and ROUTER_OP_LUT_ARP_NEXT_HOP_IP_REG. This table gives the MAC address of the next hop IP found in the Routing table.
The Routing table has the following data registers: ROUTER_OP_LUT_RT_IP_REG, ROUTER_OP_LUT_RT_MASK_REG, ROUTER_OP_LUT_RT_NEXT_HOP_IP_REG, and ROUTER_OP_LUT_RT_OUTPUT_PORT_REG. The routing table does a LPM search to find the next hop's IP address and the output port on which a packet should be forwarded. WARNING: Entries should be ordered such that the longest subnet masks are at the lowest index into the table.
The Destination IP filter table has the following data register: ROUTER_OP_LUT_DST_IP_FILTER_IP_REG. This table should have the IP addresses of the router's interfaces in addition to any IP that the router should forward to the CPU such as the PWOSPF multicast IP address.
| Bit | Bit description |
| OQ_ENABLE_SEND_BIT_NUM | Bit position in the OQ_CONTROL_REG_i to enable sending packets out of the output queues |
| OQ_INITIALIZE_OQ_BIT_NUM | Bit position in the OQ_CONTROL_REG_i to reset the output queues pointers |