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v1.1.0 — Goldilocks finite-field vector arithmetic and dot-product | Goldilocks 素域向量运算与点积
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MIT-licensed Goldilocks finite-field vector arithmetic and dot-product hardware accelerator. Chisel source and generated SystemVerilog.
Released design
| Item | Scope |
|---|---|
| Computation | ADD, SUB, MUL, FMA, weighted LINCOMB and DOT over the Goldilocks prime field |
| Bundled configuration | L up to 65,536, K up to 8, one lane; top PrimeFieldVector |
| Representation | Canonical 64-bit field elements, p = 2^64 - 2^32 + 1 |
| Native boundary | Task, coefficient/data, indexed result and completion ready/valid channels |
| Scheduling | One complete vector task at a time; pipelined elements, with bounded output credits |
Engineering evidence and integration
Project overview · Native interface · Reproduction · Performance · Synthesis scope · License
Recorded verification scope: The documented typical suite contains 104 tasks, 5,112,713 input records and 1,966,448 results. Independent C/Python references, regenerated/bundled SV comparison, ideal traffic, protocol stalls, reset recovery and a deliberate reference error are separate checks. The outer verification command requires all its expected positive and negative outcomes; a negative simulator return is not itself an overall failure.
Integration boundary: LINCOMB consumes its coefficient records first, then K consecutive data records for each output as specified in the native interface. DOT is a reduction, not an elementwise output vector. Empty DOT returns zero. This is prime-field arithmetic, not an NTT, extension-field unit or complete constraint/proof engine. The surrounding system supplies data movement and respects task-defined frame draining on errors.
Evidence applies to the documented version, configuration and target. Simulation, synthesis and board/silicon measurements are distinct. These are standalone compute blocks, not an end-to-end zero-knowledge prover.
Custom integration and licensing
For optional custom ASIC/FPGA accelerator development and integration, visit OpenRTL Lab. MIT-licensed commercial use does not require a paid engagement. Retain applicable copyright, license and third-party notices.
Release downloads
These downloads provide hardware sources and bundled RTL for this version. Archive annotations and documentation can differ from the online source tree; use the product file list for integration and the linked documents for verification scope.
OpenRTL organization · ZK accelerator catalogue
简体中文
MIT 开源 Goldilocks 素域向量运算与点积硬件加速器，提供 Chisel 源码与生成的 SystemVerilog。
已发布设计
本模块在Goldilocks素域执行ADD/SUB/MUL/FMA/LINCOMB/DOT，典型最大长度65536、最多8项、单lane。LINCOMB先输入系数，每输出消耗K条数据；DOT是归约而非逐元素输出，空DOT返回零。完整向量任务不重叠，内部元素流水；不包含NTT、扩域运算或完整证明协议。
工程证据与集成
项目介绍 · 原生接口 · 复现步骤 · 性能条件 · 综合范围 · 许可
支持配置、数学模型、测试场景、性能条件和综合结论分别以对应文档为准。仿真、综合与板级或硅后实测应区分理解，不能把某一配置的验证结论推广到全部参数或目标。这是独立计算模块，不是端到端零知识证明生成系统。
定制集成与开源许可
如需可选的 ASIC/FPGA 加速器定制开发与集成，请到 OpenRTL Lab 官方网站了解服务与联系方式。MIT 许可代码可免费用于商业用途，保留适用的版权、许可和第三方声明；付费定制与支持是独立、可选的服务。
发布下载
以上下载提供本版本硬件源码与随包 RTL。源码包与在线源码树的注释及文档可能不同；集成使用产品文件清单，验证范围以链接文档为准。