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BPU clock gating #2733
BPU clock gating #2733
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CI failed |
seems failed for no reason, just re-run for now. |
[Generated by IPC robot]
master branch:
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Behavior change is expected, but I will split the changes affecting performance into another PR. |
I believe the performance fluctuation is due to a performance bug fixed in e6b2fa7, which have minor influence. In 14 microbenchmarks, 6 decreased MPKI, 1 same, and 7 increased. I think the fluctuation is acceptable.
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re-running CI with LFSR changes reverted. |
[Generated by IPC robot]
master branch:
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[Generated by IPC robot]
master branch:
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this commit ports clock gating optimization from nanhu if applicable, most ungated register is opted Co-authored-by: Liang Sen <liangsen20z@ict.ac.cn>
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some control signal inside Tage is using data signals from io this commit add io control to these signals
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[Generated by IPC robot]
master branch:
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@Tang-Haojin I believe this can be merged? |
Need squash or rebase? |
@Tang-Haojin prefer squash, not big PR. |
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